Assignment 03: Sequential Logic & Memory

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Assignment 03: Sequential Logic & Memory

Q1 Global Deductions

0 Points

Be sure your truth tables are in order and you follow the required formatting for CircuitLab questions!

Q2 RS Latch

42 Points

Refer to the RS Latch discussed in lecture for these questions.

Q2.1 RS Latch - Timing Diagram

34 Points

Using this image as a starting point,

Complete the timing diagram above for the outputs Q and Q'. You do not need to show propagation delay for this question.

Additionally, label the 5 different “actions” of the RS-Latch on your timing diagram (one action per column). If an action appears more than once, write it each time.

You must do this in CircuitLab, export the .png image, and upload it here. We will not accept any other submission.

Q2.2 RS Latch - Action Sequences

8 Points

This is an example of an Action Sequence: SET-> HOLD.

Does your completed timing diagram cover all the action sequences that demonstrate RS-Latch functionality? If no, please explain why.

Q3 Custom Latch

58 Points

Refer to the following sequential logic circuit for the next set of questions.

This circuit is a latch. Its inputs are A and B, and its outputs are C and C'.

C and C' must be opposing values: C'= NOT(C).

Q3.1 Custom Latch - Truth Table

20 Points

Generate a truth table for the latch. Additionally, label the Actions of this latch.

Hint: similar to lecture, find a known state that doesn’t depend on the previous output to begin your analysis.

Upload a .png image of your completed truth table here. We will not accept any other submission.

Q3.2 Custom Latch - Timing Diagram

20 Points

Generate a timing diagram for the latch. Additionally, label the Actions of this latch.

Your timing diagram must cover all possibilities discussed in your truth table. You do not need to show propagation delay for this part.

You must do this in CircuitLab, export the .png image, and upload it here. We will not accept any other submission.

Q3.3 Custom Latch - Comparisison with RS Latch

8 Points

Compare this latch to the RS Latch. List two similarities and two differences

Q3.4 Custom Latch - Transistor diagram

10 Points

Implement this latch using CMOS transistors. You must show all wires to get full credit. Feedback wires are the most important!

You must do this in CircuitLab, export the .png image, and upload it here. We will not accept any other submission.

Q4 D-Flip Flops and Latches

46 Points

Refer to the circuit below for these next questions:

The main components are the four D-Flip-Flops (they are not latches).

Assume that at time 0, the DFFs initially have the data shown on the diagram stored within them (that is, 1011).

Note the ground connection creates a continuous input of 0 to the circuit which flows from left to right, and remember that DFFs store a bit in their output Q.

For your timing diagrams, use 8 grid squares (from the CircuitLab background) horizontally for each half of the clock cycle.

Q4.1 D-Flip Flops and Latches - Timing Diagram

20 Points

Complete the timing diagram below for the outputs Q3, Q2, Q1, Q0.

You must re-create the entire timing diagram in CircuitLab. You must show propagation delay for this question.

You must do this in CircuitLab, export the .png image, and upload it here. We will not accept any other submission.

Q4.2 D-Flip Flops and Latches - Bitwise/Arithmetic Operation

10 Points

Examine your timing diagram carefully: what bitwise/arithmetic operation does this hardware implement?

Hint: write out the 4-bit number saved at each clock cycle

Q4.3 D-Flip Flops and Latches - Replace with D-latches

16 Points

Replace the DFF's with D-Latches and generate a new timing diagram for this new circuit.

You must do this in CircuitLab, export the .png image, and upload it here. We will not accept any other submission.

Does this circuit function the same way as compared to what you described in part (b)? Why or why not?

Q5 Logic Circuit Analysis

10 Points

Refer to this circuit for the following questions:

Q5.1 Logic Circuit Analysis - Output when S = 0

4 Points

Describe the output of this logic circuit when the select line S is a logical 0. That is, what is the output Z for each value of A?

Q5.2 Logic Circuit Analysis - Output when S = 1

4 Points

If the select line S is switched from a logical 0 to 1, what will the output be?

Q5.3 Logic Circuit Analysis - Storage Element?

2 Points

Is this logic circuit a storage element?

Yes

No

Q6 Size of Memory

10 Points

If a computer has eight-byte addressability and needs three bits to access a location in memory, what is the total size of memory in bytes?

Enter the numeric value only.

Q7 Address vs Addressability

10 Points

Distinguish between a memory address and the memory’s addressability.

Q8 Reading from memory

10 Points

Using Figure 3.21 in your book (the diagram of the 4-bit entry, 2- by-3-bit memory), answer the following questions.

Q8.1 Reading from memory - determining inputs

5 Points

To read from the fourth memory location (at index = 3), what must the values of A[1:0] and WE be? Note that memory is zero-indexed.

A[1:0]:

Enter the two bit value here.

WE:

Enter the one bit value here.

Q8.2 Reading from memory - changing memory

2.5 Points

To change the number of entries in the memory from 4 to 60, how many additional address lines would be needed?

Enter the numeric value only.

Q8.3 Reading from memory - changing addressability

2.5 Points

What would the addressability of the memory be after this change was made?

Enter the numeric value only.

Q9 Memory circuit

10 Points

Use the memory shown below to answer the following questions.

Q9.1 Memory circuit - Address space

4 Points

What is the address space of this diagram, based on the memory shown?

Enter the numeric value only.

Q9.2 Memory circuit - Addressability

4 Points

What is the addressability?

Enter the numeric value only.

Q9.3 Memory circuit - Address space

2 Points

What is the data at address 2 (that is, A = #2)?

Enter the four bits here.

Q10 Memory calculation

10 Points

Given a memory that is addressed by 22 bits and is 3-bit addressable, how many bits of storage does the memory contain?

Enter the numeric value only.