CGS 3269 Computer Architecture Concepts Fall 2024 EXAM 2 PRACTICE

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Department of Computer Science

CGS 3269 Computer Architecture Concepts

Fall 2024

EXAM 2 PRACTICE

1. Sketch an SR flip flop & its truth table. Please explain briefly (2 sentences max) the reason why S=1 and R=1 results in Q(t+1) being undefined.

2. Design a 3-bit counter that counts from 000 to 111 using JK flip/flops. Do not forget the carry and overflow.

3. Design a D flip/flop at gate level plus its truth table.

4. A 4-bit-ring counter is used to execute the instruction in four click ticks (C1, C2, C3, C4). In your design, you must show the IR, the decoder, and a ring counter for the instructions Store and Add. Show (using a box with a label for each computer component), the part of the computer that received the signals C1, C2, C3 and C4. Don’t forget the numbers on the decoder.

5. Using a 5-stage pipelined architecture (IF-OF-EX-MEM-WB), show what stages are utilized by the instructions Add, Store and Load.

6. With the same 5-stage pipelined architecture, show the steps for: ADD R1, R3, R4 (you can use the same drawing just make sure to number your answers)

7. Convert the following numbers to floating point “tiny IEEE format” and also to the “Standard Form.” No arithmetic needed. Just show the number in both formats.

7.1 ) 127

7.2 ) 39