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EEC 180 — DIGITAL SYSTEMS II WINTER QUARTER — 2023 MIDTERM EXAM

发布时间:2024-06-12

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EEC 180 — DIGITAL SYSTEMS II

WINTER QUARTER — 2023 — 5 UNITS

MIDTERM EXAM

1  VERILOG CODING (15 + 10 = 25 POINTS)

Consider the implementation shown below.

1. Develop a Verilog structural model for the above circuit. A structural model is based on instantiations of basic modules.

2. Develop a Verilog model for the above circuit by using assign statements only.

2  COUNTERS (25 POINTS)

Consider an 5-bit counter with the following specifications:

• The counter has a synchronous input Reset and an output Count.

• If Reset = 1, the counter resets the state to 00000. Otherwise, the counter will count as follows: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, and repeat.

Write a Verilog model for the counter using 20 lines of code or less. Assume that it is the responsibility of the user of the counter to reset it before using it.

3  COMBINATIONAL ARITHMETIC CIRCUITS (10 + 5 + 10 = 25 POINTS)

Consider a combinational circuit that computes the following three arithmetic functions:

X =  2A + 1                       Y =  4A + 3                           Z  =  8A2 + 10A + 3

Let us assume that A is an n-bit unsigned number and the outputs (XYZ) are unsigned num- bers.

1. What is the minimum number of bits needed (in terms of n) for each of the outputs XY, and Z?

2. Compute the logic equation for Z0  (The least significant bit of Z)?

3. Write a verilog model for the above circuit for the case of n = 4.

4  NUMBER REPRESENTATION (7 + 8 + 10 = 25 POINTS)

In this problem, we would like to compute the decimal values of certain unsigned or signed binary numbers. For example, the decimal value for the n-bit unsigned number 111...11 is 2n – 1 . Also, the decimal value for the n-bit signed number 111...11 is –1 . Compute the decimal values of the following numbers:

Warning: The decimal value of the n-bit unsigned number 111...11 should be reported as  2n – 1 . n – 1

It is not sufficient to report the value as 2n  1 + 2n  2 + … + 21 + 20  or  Σ 2i i = 0

1. An n-bit unsigned number 0111...1110.

2. An n-bit unsigned number 101010...1010. Assume that n is even number.

3. An n-bit signed number 101010...1010. Assume that n is even number.

5  FINITE STATE MACHINES (25 POINTS)

Write a Verilog model for the finite state machine with the state diagram shown below.