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ENGI4547 Advanced Electronics 4 2021-2023
发布时间：2024-05-16
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ENGI4547-WE01
Advanced Electronics 4
2021
Question 1
Dennard scaling enabled Moore’s Law to be implemented by roughly doubling the device density per wafer for some time. However, in practice Dennard scaling could not be applied indefinitely due to a number of emergent problems.
a) Explain how Dennard scaling leads to increased gate leakage current and what solution was proposed to reduce the gate leakage current. Include a sketch, where appropriate, to explain your answer. Assuming a particular MOSFET design has a SiO2 gate insulator with thickness d = 4 nm and dielectric constant, ε = 3.9. What thickness (nm) of HfO2 dielectric (ε = 25) would give equivalent current if it replaced the SiO2? [56%]
b) Sketch and explain Electromigration and Black’s law in the view of interconnects and wiring between MOSFETs. Using Black’s law, calculate t50 of an Aluminium wire (Ea = 0.55 eV) operating at 105o C, if it has t50 of 550 hours when tested at an elevated temperature of 240o C. Assume the Aluminium wire has same current density at both the temperatures. [44%]
Question 2
Understanding charge transport mechanism in electronic devices is very important in order to make them better and faster.
a) Describe what phonons are and what impact they have on charge transport? Calculate and comment on the change in mean free path of charges in a device when it is cooled from 300K to 120K, considering the mean free path at room temperature is 40Å and phonon energy En = 20meV. [64%]
b) The mean free path of electrons in a semiconductor at 300K is 100 nm.
i) Calculate the charge carrier mobility assuming their effective mass m* = 0.065m0 .
ii) Assuming phonon energy 20meV, comment on the mobility measurement at 4K if the distance electrons have to travel is 300nm. [36%]
Question 3
Organic semiconductors can be synthesised chemically and they can be processed using low energy and low cost processing methods to fabricate electronic devices.
a) Explain the bonding arrangement in organic materials that lead to material being insulating or
able to conduct charges. Include sketches where appropriate to illustrate your answers. [56%]
b) Estimate the bandgap of a polymer containing 4 Carbon atoms connected in a linear chain of bonds of length 135 Pico meter. What number of Carbon atoms might be required for the polymer to appear to act as a metal? [44%]
Question 4
Organic thin film transistor can be fabricated through low temperature and solution processing methods using organic semiconducting and dielectric materials.
a) Explain why polarons localise the charges in organic semiconductors. Explain the hopping transport mechanism and impact of the electric field on it. Include sketches where appropriate to illustrate your answer. [56%]
b) For an ideal organic thin film transistor, using linear and saturation regime I-V relations, sketch and explain the variation of
(i) Drain-Source current vs. Drain-Source voltage (output characteristics).
Label and explain the significant regions of the graph.
(ii) Drain-Source current vs. Gate voltage (transfer characteristics). [44%]
ENGI4547-WE01/ ENGI44N10-WE01
Advanced Electronics 4
2022
Question 1
Assuming you are an electronics engineer working on scaling down the size of MOSFETs on a chip.
a) Explain (in your own words), how the scaling of the interconnect wiring between MOSFETs affects the chip performance? Identify and explain the parameters that require attention during interconnect scaling and what is the multilayer solution? Include sketches where appropriate to illustrate your answers. [60%]
b) The current generation MOSFET interconnect wiring has a pitch, P = 300 nm and number of layers N = 5
i) Suggest the number of interconnect layers in the next generation if the size is reduced versus the current generation by a scaling factor of K = 1.414? Assume that the RC time constant is kept the same.
ii) How many interconnect layers would be required to reduce the RC time constant by at least half? [40%]
Question 2
Assuming you are an electronics engineer working on development of organic semiconductor based devices using low energy and low cost processing methods.
a) Describe (in your own words), why charges would be localised in organic semiconducting thin films, and what impact localised charges have on charge transport? Include sketches where appropriate to illustrate your answers. [60%]
b) Estimate the bandgap of a polymer containing 5 carbon atoms connected in a linear chain of π bonds of length 130 picometres. What type of material would this be? And what number of carbon atoms might be required for the polymer to appear to act as:
i) A metal.
ii) A semiconductor with a bandgap of equivalent to energy associated to a photon of wavelength of 555nm. [40%]
Question 3
When it comes to the development of memory devices in a system, Random Access Memory (RAM) is built to last a long time and provide higher speed to the system in accessing the data.
a) Describe (in your own words) flash memories and the role of a floating gate in flash memories. Derive an expression to calculate the number of charge carriers that could be stored on the floating gate while limiting the charge stored on the floating gate such that the potential on the floating gate times unit charge is half of the barrier height. Include sketches where appropriate to illustrate your answers. [60%]
b) Predict the maximum number of electrons that could be stored on a flash transistor with a 20nm lateral feature, 6nm vertical features and a SiO2 dielectric. SiO2 has dielectric constant of 3.9 and barrier height of 3.1 eV. With reference to your answer, explain the consequences the next generation of CMOS scaling (i.e. scaling factor 1.414) will have upon flash memory performance. [40%]
Question 4
Electronic devices, those that are truly nanometre scale, are emerging device types and their operation differs from conventional silicon technology.
a) Describe (in your own words) the advantages, requirements and limitations of ‘single electron devices’ in order to write a bit of information at room temperature. Include sketches where appropriate to illustrate your answers. [56%]
b) What would be the charging energy and diameter of the sphere? Assuming it has a capacitance of 6.67×10-17 F, when suspended in free space. Could the conductivity of a transistor incorporating this island be controlled at room temperature? Could it be controlled if the island had a 16 nm diameter? What are the consequences of cooling it to liquid He temperature? [44%]
ENGI4547-WE01/ ENGI44N10-WE01
Advanced Electronics 4
2023
Question 1
A) Describe (in your own words) how Dennard scaling has enabled Moore’s Law to be implemented. Include a sketch of a planar MOSFET before and after Dennard scaling. [8%]
B) Calculate the scaling factor for the transit time and gate capacitance in a planar MOSFET if the Dennard scaling factor is K, where (K > 1). [17%]
Question 2
A) Assuming you are an electronics engineer working on the development of organic semiconductor-based devices using low energy and low-cost processing methods. Discuss (in your own words) the electronic structure / the origin of free carriers in organic semiconductors and the origin of the bandgap in such materials. [12%]
B) i) Estimate the bandgap of a polymer containing 5 carbon atoms connected in a linear chain of π bonds of length 130 picometres. ii) What type of material would this be? iii) And what number of carbon atoms might be required for the polymer to appear to act as a metal? [13%]
Question 3
A) Describe (in your own words) the ‘single-electron transistor devices’ and their requirements in order to write a bit of information at room temperature. [12%]
B) What would the charging energy be for a sphere, of 1.2 µm diameter, assuming it is suspended in free space? Could the conductivity of a transistor incorporating this island be controlled at room temperature?
Could it be controlled at liquid He temperature? [13%]
Question 4
A) Describe (in your own words) the role of a floating gate in flash memories. [12%]
B) i) How many electrons could be stored in a Flash transistor using a 6 nm thick SiO2 dielectric, with a lateral dimension of 20 nm? ii) If this floating gate was charged to its maximum capacity, what total leakage current would be permissible for a data lifetime of 12 years? [13%]
