ELEC372/472 INTEGRATED CIRCUITS - CONCEPTS AND DESIGN Assignment 1

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ELEC372/472

INTEGRATED CIRCUITS - CONCEPTS AND DESIGN

Assignment 1

Assignment 1: Effect of parasitic capacitance

Question 1:  [10/100]

Write a basic description of the task. You can refer to the lecture notes for details of derivation (don’t reproduce it all!).

Question 2:      [15/100]

Briefly describe the APPROXIMATIONS assumed in the analysis.

Question 3  [20/100]

Include a graph of the Fall-time as a function of width, W. Use sensible range of values e.g. you can not drive many gates at high speed. Explain your graph/observations in the text box below the graph.

Question 4:      [20/100]

Include a graph of Fall-time as a function of fan-out (i.e. attach an increasing number of inverters to the test inverter); choose one value of W.  Explain your graph/observations in the text box below the graph.

Question 5:     [20/100]

List all your calculated device capacitance and other parameters. Which is the largest capacitance component?  (remember how you should quote the values!)

Question 6:   [15/100]

Please paste your source code below. (If you right-click, paste options you choose to can keep the format as in, e.g. Matlab)