CSE 560 – Practice Problem Set 4 Solution

Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: daixieit

CSE 560 – Practice Problem Set 4 Solution

1.    Use the following RISC code fragment:

(1)    loop:       load        r1, 0(r2)

(2)                    addi        r1

(3)                    store       0(r2), r1

(4)                    addi        r2

(5)                    sub          r4

(6)                    bnez        r4, loop

(7)                    next instruction

You may assume that the initial value of r3 is r2 + 396.

(a)  Show the timing of this instruction sequence (i.e., draw a pipeline diagram) for our 5-stage

pipeline without any forwarding or bypassing hardware but assuming a register read and a   write in the same clock cycle “forwards” through the register file.  Assume that the branch is handled by flushing the pipeline (use the notation f in the pipeline diagram).  If all memory   references hit in the cache (i.e., take one cycle), how many cycles does this loop take to         execute?

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

(1)

F

D

X

M

W

(2)

F

D

d*

d*

X

M

W

(3)

F

p*

p*

D

d*

d*

X

M

W

(4)

F

p*

p*

D

X

M

W

(5)

F

D

d*

d*

X

M

W

(6)

F

p*

p*

D

d*

d*

X

M

W

(7)

F

p*

p*

D

f*

(1)

F

D

17 – 1 cycles = 16 cycles to execute

(b)  Show the timing of this instruction sequence for our 5-stage pipeline with normal

forwarding and bypassing hardware.  Assume that the branch is handled by predicting it as  not taken.  If all memory references hit in the cache, how many cycles does this loop take to execute?

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

(1)

F

D

X

M

W

(2)

F

D

d*

X

M

W



2022-10-17