Objective

To understand fundamental concepts underlying CMOS gate speed performance.

Assignment description

The task is to perform basic calculations on the switching speed of a CMOS inverter, as defined by the propagation delay from high to low, τpHL,

TpHL  = () { + ln [ − 1]}

and to investigate how the propagation delay from high to low is affected by:

a)   the size (width) of the transistors

b)   the fan-out of the inverter

c)  the power supply voltage

d)   the channel length

For all conditions investigated in this assignment, the p-channel transistor should be sized to maintain the condition that propagation delay from high to low = propagation delay from low to high (τpHL = τpLH).

The required theory has been presented in the lectures. The equations assume that long channel theory is applicable in our case (discuss this in your report and take care not to violate this assumption when investigating the effect of channel length and width).

Such calculations are extremely useful prior to performing simulation tasks, as the values obtained from a simple model will provide information on how to set up the simulation – that is, will establish the time frame of interest and allow the frequency of the test signals to be determined so that all the expected behaviour is investigated. The equations also give insight into the relevant circuit and device parameters and their expected effect. Finally, it is reassuring to check that the results obtained from the simulation packages are reasonable.

Because of the large number of calculations involved, you will be expected to write a short computer programme to produce the results. You may use whichever computer programme you prefer, but it is essential that the programme is well documented and accompanied with a flow chart that lists the constants used, the equations solved and the order of their solution. The programme itself should be well commented and be consistent with the flow chart. The computer program should be regarded as a tool with which to obtain the results. It does not, in itself, constitute an objective of this assignment, but a professional approach is essential and marks will be deducted for incomprehensible computer listings.

You should think about which parameters to define as variables and which as constants - for example transistor width (W), needs to be defined as a variable (see below).

To develop the model for the effective capacitor load (CL), please refer to the lecture notes and also the information provided in the appendices to this script. The values given have been extracted from the SPICE models for the transistor technology that you will use in the later assignments.

Take great care with units – best practice is to convert everything to SI units. Values in SPICE are not always quoted in SI units so you may need to convert some values. Check that the values you are getting for parameters are sensible – for example, what value do you expect for the built-in voltage of a p-n junction?

Once your simple (don’t look for complications!) programme is running and yielding sensible values, plot graphs to show:

1.  τpHL vs Wn with channel length Ln = Lp = 1 μm, VDD = 2.5 volts and with a single identical inverter (i.e. same as that of the driver) as the load.

2.  The effect of ‘fan out’ on switching speed - assume n identical inverter stages, attached to the output.

3.   The effect of the supply voltage on switching speed over a sensible range (remember that the analysis assumes VT0n > 0.1VDD).

4.   Repeat parts 1, 2 and 3 above for channel length = 2μm and 3μm all with Ln = Lp .

Consider carefully how your plots should be organised to allow an easy comparison. e.g. plot a family of associatedplots on one graph with common axes.

Also choose carefully the range of W and VDD over which you calculate the propagation delay from high to low so that the significant trends are investigatedfully.

Refer to the  information provided in Appendix 2  concerning the  SPICE parameters  for the transistors to be used in the circuit and some initial constraints. Note that the parameters are extracted from a BSIM3 model that is able to take into account short channel effects should the channel length be small enough. However, the analysis ignores short channel effects, so your results should not involve channel lengths or widths less than 1 micron. This means that many of the parameters of the full BSIM3 model are not relevant to the present exercise and are not listed here. You will use the full (extensive!) parameter listing later in the module.

The Report

The report should consist of three sections and two appendices:

Section 1: ( 1 page maximum).

A basic description of the task. You can refer to the lecture notes  (but don’t reproduce the derivation of equations). You should comment on the validity of the approximations made in the analysis

Section 2:

The results obtained from your programme (in graphical form) clearly labelled and identified with the value of the parameters used.

Section 3: (2 pages maximum)

An explanation of the results together with comments and conclusions.

Appendix 1: Equation listings – list/derive  logically  all  equations which you used  for your

programme.

Appendix 2: Flow charts and code listings – well documented. Comment also on your choice of programming language / software package(s).

Submission date

The report must be submitted (e-copy electronically through Learning Mall) by 23:00 on Friday 14th October 2022

Assessment

This assignment contributes 10% to the overall module mark for EEE337.

Marks for this assignment will be awarded as follows:

Section 1             20%

Section 2             20%

Section 3             30%

Appendix 1+2     20%

Overall standard of presentation 10%

Notes for guidance

1)        You are required to use a word processor in preparing reports which  should be well presented and have a good standard of English. Graphs etc should have meaningful titles, axes should be labelled correctly and include appropriate units. A professional standard is essential - you may find the reports useful later in your future job interviews. Marks will be lost if the expected high standard of presentation is not met. Remember: it is the QUALITY of what you write that earns the marks, not the QUANTITY !!

2)        Use your notes from EEE337 to help you understand what you are doing. You may also find Chapter 3 in the recommended textbook (CMOS Integrated Circuits by Kang and   Leblebici) useful.

3)        Quote all numerical values in SI units using appropriate prefixes:

10-3 = milli = m

10-6 = micro =

10-9 = nano = n

10- 12 = pico = p

10- 15 = femto = f

e.g.:

BAD - A capacitance quoted as ‘2.3456256E- 13’

WHY? – No units, not in SI, too many decimal places

This conveys to the reader that you have pressed buttons on a calculator and have no real understanding of what you are doing.  What do you expect the capacitance

values to be – nF? pF? (check in a book if you are not sure)

GOOD: quote either as 0.23 pF or more precisely as 235 fF.

ALWAYS THINK ABOUT THE VALUES YOU GET - ARE THEY

REASONABLE?

4)        Note that some SPICE capacitances have units of ‘farads per unit width’ or ‘Farads per unit area’ and so must be multiplied by the appropriate dimensional parameter to obtain the actual capacitance.

5) The Miller effect, which will be used in Appendix 1, is illustrated in Figure A1.

Appendix 1: Calculation of the effective load capacitance CL

(See also section 3.6 of CMOS Integrated Circuits by Kang and Leblebici)

VDD

Cg4

M2

Cdbp

Cgdp

Cgdn

Cint

Cdbn

M1

Cg3

VSS

Figure A2 – Unity fan-out inverter

The figure A2 shows a CMOS inverter loaded with another inverter together with the important internal capacitances that affect the output of the first inverter (node Vo1). To allow an estimate of the switching time using the transient model derived in the EEE337 lectures, we seek an effective load CL  that can be placed on the output of the first inverter to represent the device internal capacitances and wiring capacitance shown. These capacitances are:

where ADn, p       =   Area of the drain (= Y × Wn, p where Y is the length of the drain diffusion

and W the channel width. Use a constant Y = 1μm for these calculations). PDn, p      =   Side wall (perimeter) of the drain (= 2Y + 2Wn, p).

Wn, p      =   width of the channel

Ln, p         =   length of the channel

and CGDO, CGSO, CGBO, CJ, CJSW are SPICE parameters given in Appendix 2 and Cox is the gate oxide capacitance per unit area.

Note that the Gate-Drain overlap capacitances need to be multiplied by two due to the Miller Effect.

keqn,p   is  a  factor that takes  account  of the voltage  dependence  of Cdbn,p ;  it is related to the capacitance of the depletion region associated with the drain/substrate junction.

Recall that a pn junction depletion capacitance can be written as:

Cj = A ))||(Vbi 一 Va )一1           or Cj = 1 A一o))||0.5 (A1)

where Va is the voltage across the junction, Vbi is the built-in voltage of the junction, Cjo is the     zero bias capacitance of the junction (i.e. Va = 0) per unit area and NA, ND are the average doping levels of drain and substrate regions. Note also that:

Vbi = 0.025ln ))||    at 300。K                              (A2)

where ni is the intrinsic carrier concentration = 1.5 x 1016 m-3  at 300 。K.

The non-linear capacitance Cj given by Eqn. A1 can be conveniently written as an equivalent large signal capacitance Cjeq such that for a given voltage swing, the same amount of charge is switched. It can be shown that:

Cjeq = A . Cjo keq CJ  >Cjo in SPICE                 (A3)

where keq is a dimensionless coefficient given by:

keq = ( VH(2)V一V(bi)L ) [Vbi + VH 一 Vbi + VL ]必 keq (sw)                                                                             (A4)

where VH and VL  represent the voltage swing of interest - in our case the VDD and 0.5VDD levels because of τpHL .

Note that there are a number of approximations made in estimating load capacitance in this way. The SPICE simulation of course, uses much more accurate models for the capacitances.