CEG 3155: Digital Systems II (Fall 2022)
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CEG 3155: Digital Systems II
(Fall 2022)
Assignment #1: Logical Function Optimization
Question I
This question is about the optimization of logical functions using algebraic ma- nipulation. Parts a, b, c and d are questions 2.10, 2.11,2.54 and 2.56 of your manual.
Part a
Use algebraic manipulation to show that for the three input variables x1 , x2 and x3
m(1, 2, 3, 4, 5, 6, 7) = x1 + x2 + x3 (1)
Part b
Use algebraic manipulation to show that for the three input variables x1 , x2 and x3
m(0, 1, 2, 3, 4, 5, 6) = x1 . x2 . x3 (2)
Part c
Design the simplest circuit that realizes the function f (x1 , x2 , x3 ) = using NAND gates only.
Part d
Design the simplest circuit that realizes the function f (x1 , x2 , x3 ) = using NOR gates only.
m(3, 4, 6, 7)
m(3, 4, 6, 7)
Part e
Determine whether the following boolean functions are equal or not:
g(x, y, z) = x . y + x . y + x . y . z (4)
Question II
This question is about synthesis with multiple outputs and levels. Review sec- tion 8.1 and 8.2 of your manual to help you. Parts a and b are questions 8.7 and 8.9 of your manual.
Part a
Find the simplest realization for the function f (x1 , ..., x4 ) = m(0, 3, 4, 7, 9, 10, 13, 14),
assuming that the logic gates have a maximum fan-in of two.
Part b
Use the functional decomposition to find the best implementation for the func-
tion f (x1 , ..., x5 ) = m(1, 2, 7, 9, 10, 18, 19, 25, 31) + d(0, 15, 20, 26). How does
your realization compare with the cheapest SOP realization? Provide the costs.
Part c
Use a Karnaugh map to minimize the next function boolean
f (a, b, c, d, e) = m(4 , 5 , 10 , 11 , 15 , 18 , 20 , 24 , 26 , 30 , 31) + d(9 , 12 , 14 , 16 , 19 , 21 , 25) (5)
Consider the following functions:
f1 = m(0, 2, 4, 5, 9, 10, 11, 13, 15) (6)
f2 = m(2, 5, 10, 11, 12, 13, 14, 15) (7)
f3 = m(0, 2, 3, 4, 9, 11, 13, 14, 15) (8)
Minimize these functions and realize them in a single least costly common circuit.
Question III
This question is about components of combinatorial circuits. Parts a, b and c are questions 4.7, 4.8 and 4.23 of your manual.
Part a
Consider the function f = w2 + w1 . w3 + w1 . w3 . Show how the repeated application of Shannon’s expansion can be used to derive minterms of f .
Part b
Repeat part a for f = w2 + w1 . w3 .
Part c
Derive the circuit of an 8-to-3 priority encoder.
Part d
Perform the following functions using a 3-to-8 decoder:
f2 (a, b, c) = a . b + a . b (10)
Part e
Make a 6-to-64 decoder using four 4-to-16 decoders and one 2-to-4 decoder. Use A5 A4 A3 A2 A1 A0 as data and D0 _ D63 as outputs. Remember the signal Enable for each decoder.
This question relates to VHDL at the structural level. The parts a, b and c are question 4.26, 4.27 and 4.29 of your manual.
Part a
Create an entity in VHDL called if2to4 which represents a binary 2-to-4 decoder, using an if-then-else expression. Give the VHDL code at the behavioral level. Create a second entity in VHDL called h3to8 which represents the binary 3-to-8 decoder shown in Figure 4.15, using two examples of the if2to4 entity. Write the code in VHDL at the structural level.
Part b
Create an entity in VHDL called h6to64 which represents a 6-to-64 binary de- coder. Use the treelike structure in Figure 4.16, in which the 6-to-64 decoder is constructed using five examples of the h3to8 decoder created in the problem in part a. Give the VHDL code at the structural level.
Part c
Design a shift circuit, similar to the one in Figure 4.51, which can shift a vector of four input bits, W = w3 w2 w1 w0 , a one bit position to the right when the Ri这ht control sign is equal to 1, and a one bit position to the left when the Left control signal is 1. When both are 0 (Right = Left = 0), the circuit efficiency should be the same as the input vector. Suppose the condition Ri这ht = Left = 1 will never occur.
Question V
This question relates to the ASM method. Review Lessons and Lab #1 to get a deeper idea of this technique of systematically designing digital circuits. A four-bit counter should be designed to count in the following order: 0000 → 0001 → 0011 → 0010 → 0110 → 0111 → 0101 → 0100 → 1100 → 1101 → 1111 → 1110 → 0000 → etc. The counter starts at the state 0000 and when the command singal START is ON.
Part a
Give the pseudo-code of that counter.
Part b
Using the pseudo-code above, your task is to design and demonstrate the ASM diagram (in graphic format), the datapath, the detailed ASM diagram (in graph-ical format) and the controlpath performed with the method of a state flip-flop. Note that you can take the output of the counter as the output of a set of 1-bit registers.
Bonus Question
Show that if two 2’s complement numbers are added, the overflow bit is the XOR of the carry-in and carry-out of the most significant bit (MSB).
2022-10-03
Logical Function Optimization