SECTION A: Attempt BOTH questions [50 marks]

Q1       Consider the circuit shown in Figure Q1

Figure Q1

(b)       The propagation delay for the inverter can be written as

tpd  ≈  .

You are given that F = 2 × 10 −3A V−2, VDD  = 1.2 V, k = 2.4 .

(i)        Show that this can also be expressed in the form t = M C, where M is a resistance. What is the value of this resistance?                                  [2]

(ii)       Calculate the delay associated with the inverter in the circuit shown in

Figure Q1.                                                                                           [3]

(c)       Explain why the rising and falling delays at X are not in general equal. Why might this be a problem? What tools does the VLSI designer have to address this?                                                                                                                  [7]

(d)       Discuss  the  relationship  between  crosstalk  and  capacitive  coupling  in  the context of VLSI interconnects. Give examples of situations where each is important. What strategies are available for reducing their impact?               [7]

Q2       (a)

(b)

(c)

(d)

Consider Figure Q2.

(i)        What logical expression does this circuit evaluate and to what family of logic does it belong?                                                                            [3]

(ii)       Redraw the figure labelling the inputs and outputs.                            [3]

Figure Q2

T size the transistors for the situation where the gate in Figure Q2 is used as an input  stage within  a time-critical  combinational  logic block.  Explain your reasoning.                                                                                                         [6]

Sketch  a pre-charge  logic  circuit  which  will  accomplish  the  same  logical

function compactly. Give reasons for your design choices.                            [5]

Draw a stick diagram for your circuit from part (c). Clearly label each part of your diagram. Coloured pens or pencils may be used, but are not essential.  [8]

SECTION B: Attempt BOTH questions [50 marks]

Q3       (a)

Complex MOS ICs, such as microcontrollers, require on-chip data conversion capabilities using only MOSFETs and capacitors. A weighted capacitor digital- to-analog converter (DAC) is a good example of such a DAC.

(i)        You are asked to design a 4-bit weighted capacitor DAC and told that the input capacitance of the available operational amplifier (OPAMP) buffer is 4 pF. Briefly explain the principle of operation of this DAC and then determine the required capacitor values if the OPAMP input capacitance forms part of the DAC circuit.                                         [8]

(ii)       What is the output voltage when the digital input is  1001, and the

reference voltage VREF = 5 V?                                                             [2]

(b)       Binary weighted DACs such as the one in part (a) are limited to a resolution of

8 bits.

(i)        State and explain the reasons for this limitation.                                 [4]

(c)       The weighted capacitor DAC is also often used as a key building block in on- chip analogue to digital converters (ADC). If 8-bit resolution is desired and the system clock is 2 MHz, specify the bandwidth limits of an analogue signal which can be digitized by such a DAC-based ADC.                                       [5]

Q4       (a)

The circuit in Figure Q4 is a key building block in high-speed analogue to digital converter (ADC) design.