Your task is to implement 16-bit ripple carry adder using Verilog HDL and analyze it by            simulating it in ICARUS Verilog on timberlake.  A functional (zero delay) simulation should be used to verify the circuits works properly and a unit gate delay model simulation should be used to evaluate performance. Structural (not behavioral) Verilog must be used.  The circuit that      should be implemented is what is in the lecture notes on Verilog and digital logic.  Circuit          diagrams are shown below for your convenience.

A15 B15      A14 B14

COUT   

S15

A1 B1        A0 B0

CIN

S1           S0

Simulation & Analysis

A written report must be submitted which includes functional (zero delay) simulation results       proving that the adder works properly, the gate cost (number of gates) of your circuit, and a         detailed delay analysis.  The functional simulation must include five simulation runs that provide compelling evidence that your circuit works properly.  Compelling evidence constitutes testing   the adder over the entire range of inputs.  Testing cases such as 1+2, 3+1, 4+0, 6+2, and so on     don’t provide compelling evidence as they do not test the upper order bits of the adder.  Each test

case should be accompanied by comments that describe why the test case was chosen.  The         detailed delay analysis must show the critical path of the circuit and report the critical path delay. The analysis should report the delays associated when each of the input patterns used to prove     your circuit works are simulated under the unit gate delay model.  The average delay across all    five of these patterns must be reported, along with an analysis of the average delay.  This             analysis should indicate if the average delay is less than the critical path delay or equal to it, and  why.  Finally, the delay analysis must also include a data set that, when simulated under the unit gate delay model, has a delay greater than half that of the critical path delay, and one that is less  than half of the critical path delay.  Finding input patterns that generate such delay will help you gain a better understanding of delay.  The following checklist will help ensure that you have        included all the required components with your report.

•    Functional simulation results with five data sets proving your circuit works properly.  When submitting your Verilog source files for the project, the Verilog code associated with this     functional simulation should be calledfunctional_simulation.v).

•    Gate cost of the adder.  In other words, how many gates are in the adder?

•    Critical path of the adder under the unit gate delay model.

•    Critical path delay of the adder under the unit gate delay model

•   Unit gate delay simulation results for the adder, showing the delay for each of the input patterns used in the functional simulation.

-     At least one must result in a delay that is greater than 50% of the critical path delay.

-     At least one must result in a delay that is less than 50% of the critical path delay.

-     When submitting your Verilog source files for the project, the Verilog code associated with this functional simulation should be called unit_gate_delay_simulation.v).

•    The average delay of the unit gate simulation in the previous step.

•   Analysis of the average delay indicating if it is less than or equal to the critical path delay and why.

Real World Analysis

Case #1

You provided simulation with compelling evidence that your circuit works properly.  Consider the            importance of this step in terms of a real world example.  Circuits, like the one you implemented, are used in embedded systems that can have deadly consequences if designed improperly.  Discuss the best way to test your circuit to maximize the likelihood that it works properly along with the impact if it is not             functioning properly.  In doing so, consider the case whereby your circuit is to be utilized in the                 embedded systems that control a passenger aircraft.

Case #2

Now that you have witnessed first hand how delays propagate through a circuit, consider that Apple is      transitioning from the Intel 80x86 based architecture to the ARM based M1 processor.  The M1 processor is a system-on-chip (SOC) architecture, reducing the physical size of the hardware by incorporating the    circuitry onto a single chip.  Research the impact that these architectures have on power consumption and the environment.  Analyze and compare the two architectures based on your research. Present your           argument on which is better.