CS 147 Exam 2 Review
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CS 147 Exam 2 Review
Exam 2 includes all topics in Lecture 07 through Lecture 15, except Lecture 12 (VHDL).
1. Suppose we are using an accumulator architecture. Several memory addressing modes are available to load the contents of memory to the accumulator.
The instruction LOAD_DIR uses the direct mode.
The instruction LOAD_INDIR uses the indirect mode.
The instruction LOAD_IMM uses the immediate mode.
The instruction LOAD_REG uses the register mode.
The instruction LOAD_REG_INDIR uses the register indirect mode.
Suppose that the memory at location 5 contains the number 16.
Suppose that the memory at location 7 contains the number 12.
Suppose that the memory at location 16 contains the number 8.
Suppose that register 5 contains the number 7.
What number would be loaded into the accumulator if the instruction is LOAD_DIR 5? Answer: __________________
What number would be loaded into the accumulator if the instruction is LOAD_INDIR 5? Answer: __________________
What number would be loaded into the accumulator if the instruction is LOAD_IMM 7? Answer: __________________
What number would be loaded into the accumulator if the instruction is LOAD_REG 5? Answer: __________________
What number would be loaded into the accumulator if the instruction is LOAD_REG_INDIR 5? Answer: _________________
2. We have an Instruction Set Architecture and Implementation as described in the lecture notes and textbook (reproduced on supplementary handout). The instruction being executed (that is, the instruction at memory location 45) is 1100000 110 001 011. What is the control word? (Give the values of the control signals below.)
DA _________
AA _________
BA _________
MB _________
FS ________
MD _________
RW _________
MW_________
PL _________
JB _________
BC _________
Suppose the values of the registers are currently:
R0: 00000100
R1: 00000101
R2: 00000000
R3: 00011100
R4: 00000000
R5: 00000110
R6: 00010100
R7: 00110100
What is the value of the PC after running this instruction?
Next PC: ________
2A. We have an Instruction Set Architecture and Implementation as described in the lecture notes and textbook (reproduced on supplementary handout). The instruction being executed (that is, the instruction at memory location 45) is 1110000 110 001 011. What is the control word? (Give the values of the control signals below.)
DA _________
AA _________
BA _________
MB _________
FS ________
MD _________
RW _________
MW_________
PL _________
JB _________
BC _________
Suppose the values of the registers are currently:
R0: 00000100
R1: 00000101
R2: 00000000
R3: 00011100
R4: 00000000
R5: 00000110
R6: 00010100
R7: 00110100
What is the value of the PC after running this instruction?
Next PC: ________
3. Single cycle computer timing
We have an Instruction Set Architecture and Implementation as described in the lecture notes and textbook. Suppose that the components have the following propagation delay times.
Register: 3ns
4- 1 Multiplexer: 3 ns
2- 1 Multiplexer: 2 ns
ALU: 6 ns (Assume that all ALU operations, no matter how simple, take 6 ns)
Shifter: 2 ns
Zero detect: 1 ns
2-4 Decoder: 2 ns
AND Gate: 1 ns
Branch Control: 2 ns
Instruction Decoder: 2 ns
Zero fill: 1 ns
Extend: 1 ns
PC : 3 ns
Memory access: 12 ns
Assume that the PC and the Registers use the same clock. Assume also that the PC and the registers have the following set-up and hold times:
Set-up time: 2 ns
Hold time: 1 ns
What is the minimum clock period possible for the computer?
4. Suppose the instruction opcodes and formats are as follows:
Instruction Opcode Format Operation
LDdir 000 AD ACC M[AD]
LDindir 001 AD ACC M[M[AD]]
LDimm 010 OP ACC OP
LDrel 011 AD ACC M[PC+AD]
LDindex 100 RA OP
LDreg 101 RA ACC R[SA]
LDregindir 110 RA
(a) Write the Operation for Ldindex and Ldregindir (for indexed and register indirect addressing) Suppose the instruction format is as follows:
15 13 12 10 9 0
|
Opcode |
RA |
AD/OP |
Suppose the memory is:
Suppose the registers have the following values:
R0: 00000000 00000001
R1: 00000000 00000110
R2: 00000000 00110000
R3: 00000000 00000010
R4: 01000000 01011100
R5: 00111010 00001110
R6: 00100111 00011010
R7: 00111010 00000001
Suppose we have the following instruction at memory address 2:
011 010 000000001
(b) What value gets loaded into the accumulator after executing this instruction?
5. Suppose we add the following instruction to the Instruction Set we use for this class (given in Lecture 10 and the Supplementary Reference).
Name Description Format Action
BEQ Branch ifequal RA,RB,AD Branch ifR[SA] = = R[SB]
Suppose we execute the following instruction: BEQ R3 R5 4
(Assume that this instruction has some opcode which will be decoded by the Instruction Decoder, and that somehow the instruction can specify RA RB and AD correctly, ignoring the fact that AD and RB use the same bits. Hence, for BEQ, we only send Instruction[8:6] to the PC instead of the usual Instruction[8:6 || 2:0])
State the control signals:
AA _____
BA _____
DA _____
MB _____
MW _____
RW _____
FS _____
MD _____
PL _____
JB _____
BC _____
6. Implement (draw the circuit of) the PC component of the “Control and Datapath” on Slide 13, Lecture 07: Control Word.
Inputs:
BA: 32-bit branch taken address offset (representing a signed number)
JA: 32-bit jump address
S: 2-bit code from the Branch Control (Note: The following are different from Lecture slides)
00 means next PC ← PC + 1
01 means next PC ← PC + branch taken address offset
11 means next PC ← jump address
Output:
PC: The 32-bit address of the instruction
Components you can use:
32-bit register
32-bit adder (inputs A, B, and carry_in; outputs F and carry_out; A, B and F are 32 bits) 4-to- 1 32-bit multiplexer
2-to- 1 32-bit multiplexor
7. Suppose we add the following instruction to the Instruction Set we use for this class (given in Lecture 10 and the Supplementary Reference).
Name
STPC
Opcode Description 0001111 Store PC
Format
RA
Action
R[SA] ← PC
Format (which bits of the instruction map to each part)
15 9 | 8 6 | 5 3 | 2 0
Opcode | | SA |
Example: STPC R2
The value in the PC gets stored into Register 2.
How would you change the CPU (Control, Datapath, and generation of Control Word) circuit so that the above instruction executes correctly? Of course, all the existing instructions should also still execute correctly. Draw the new CPU circuit (just the parts that changed).
8. Draw the combinational circuit of a shifter that has two inputs: ( 1) 2-bit SHIFT, and (2) 4-bit D. This shifter has one output: 4-bit Q.
If the SHIFT input is 00, the output Q is the input D.
If the SHIFT input is 01, the output Q is the input D shifted right by one bit, and shifts in a 0 in the left-most (most significant) bit.
If the SHIFT input is 10, the output Q is the input D shifted left by one bit, and shifts in a 0 in the right-most bit.
9. Hazards
Assume that you are running the Instruction Set shown in class.
Suppose that your program contains the following section of code:
ADD R3 R2 R1
SUB R1 R2 R3
Is there a data hazard? If yes, say which register has a data hazard.
10. Control hazard
We have a pipelined datapath. Assume that when there is a control hazard (that is, whenever there is a conditional branch instruction), the two following instructions after the branch would be executed regardless of whether the branch is taken because they have been loaded into the pipeline before the branch decision is known. To mitigate that, we can either try to reorder instructions or, if that is not possible, insert NOPs (MOVA R0 R0).
Suppose we have the following program:
ADD R1 R2 R3 (This means R3 ← R1 + R2. In other words R3 is the destination register.)
ADD R3 R4 R5
ADD R1 R3 R4
BRN R5 3 (This means if content of R5 is negative, next instruction to execute is PC + 3.)
SUB R1 R2 R3
SUB R1 R4 R5
SUB R6 R7 R8
Reorder instructions or insert NOPs to make sure the pipeline works correctly, with the minimal increase to time needed to run the program.
2022-04-16