Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: daixieit

COMP4300

LabExerciseTwo

Objective

Thislabdevelopsthefirstbuildingblock fortheAubieCPU,thearithmetic-logicunit (ALU).Itwillbecombinedwiththeotherdatapathcomponentsfromlaterlabs,          resultinginacompleteCPU byLab4.

 

Instructions

DevelopVHDLforthefollowingcomponent.Youshoulddefine anarchitecturefor    theALU entitygivenbelow.Youshouldtestyourarchitecturebydeveloping              simulationfilesfortheentity.Yourarchitectureshouldimplementthefunctionality describedin thisdocument.Tomakethesimulationresultsmorereadable,wewill   usea 32-bitdatapath.

Youshouldusethetypesfromthepackage“dlx_types”(availableonthefilessection ofCanvas)  andtheconversion andmath routinesfromthepackage“bv_arithmetic” infilesbva.vhd,andbva-b.vhdonCanvas.Thepropagation delaythroughtheALU     shouldbe 15 nanoseconds.

Arithmetic-Logic Unit This unit takes in two 32-bit values, and a 4-bit operation code that specifies which ALU operation (eg. add, subtract, multiply, etc) is to be performed  on the two operands. For non commutative operations like subtract or divide, operand1  always goes on the left of the operator and operand2 on the right.

 

The operation codes are

 

0000 = unsigned add

0001 = unsigned subtract

0010 = two’s complement add

0011 = two’s complement subtract

0100 = two’s complement multiply

0101 =  two’s complement divide

0110 = logical AND

0111 = bitwise AND


1000 = logical OR

1001 = bitwise OR

1010 = logical NOT of operand1 (ignore operand2)

1011 = bitwise NOT of operand1 (ignore operand2)

1100- 1111 = just output all zeroes

 

The unit returns the 32-bit result of the operation and a 4-bit error code. The meaning of the error code should be

 

0000 = no error

0001 = overflow

0010 = underflow

0011 = divide by zero

 

The ALU should be sensitive to changes on all the input ports.  Note that the ALU is purely combinational logic, no memory, and that there is no clock signal.

 

The entity declaration is

 

entity   alu   is

port(operand1,  operand2:   in  dlx_word;  operation:   in

alu_operation_code;

result:  out  dlx_word;  error:  out  error_code);

end  entity   alu;


Deliverables

Pleaseturninthefollowingthingsforthislab:

1. ThetextofyourVHDLsourcecode.

2. Yoursimulationtestfile.Donotexhaustivelytestthesedesignssincetheytake     lotsofinputbits,butdotestareasonablenumberofthings.  Forexample,testboth normalfunctionandanerror,ifapplicable(e.g.overflowforaddu,nothingfor          and/or/not)foreachofthealuoperations.

3. Transcriptsoftestsorscreenshotsrunningyoursimulations.Itshouldbeclear     whatisbeingtested.Ifnot,addtexttoexplainit. Youcannottestexhaustivelybut     youshouldtesteachfunctioncodeforcorrectoperationanddemonstratehoweach errorcodeisgenerated.

PleaseturninallfilesonCanvas.IfIhavequestions,Imayaskyoutoschedulea   timetodemoyourcode,ifIcan'tfigureouthowsomethingworksbyreadingthe

code.