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In this assignment you will work on a combination circuit design with a real-world application. It will involve applying all the techniques you have learnt over Weeks 1-4 in the course.

The gate input cost should be calculated for the simplified AND-OR-NOT expressions in the design that you implement. You can choose the technology to implement the circuit with (e.g. AND/OR, NAND, multiplexers, etc.). However, your design for each module should aim at achieving optimized implementation. You must implement your design using structural modelling only in Verilog HDL in Vivado or other online Verilog simulators. Simulate your design using the Vivado simulator (or equivalent simulators) and validate its functionality through appropriate test benches.

Your final submission should include your design procedure, choice of technology implementation, and simulation results (screenshots are adequate for simulation results). Combine all scanned copies of your handwritten work and electronic documents into one pdf file for the submission on Moodle. This includes all design and simulation materials such as schematic diagrams (hand-drawn or electronic), Verilog modules, simulation outputs and testing fixtures.

You will need to separately submit your Verilog code for autotesting. See the final page for file naming convention and required port names. Note that you still need to include screenshots of your code in your report.

You may use online k-map solvers to solve k-maps with more than 4 variables, provided you cite the website.

Any output of generative AI software used within your assignment must be attributed with full referencing. If the outputs of generative AI such as ChatGPT form part of your submission and is not appropriately attributed, it will be regarded as serious academic misconduct and subject to the standard penalties, which may include 00FL, suspension and exclusion.

*To cite: OpenAI (Year Accessed). ChatGPT. OpenAI. https://openai.com/models/chatgpt/

Please note that the outputs from these tools are not always accurate, appropriate, nor properly referenced. You should ensure that you have moderated and critically evaluated the outputs from generative AI tools such as ChatGPT before submission.

JOEXAPE is a startup based on escape rooms designs. However, the escape room market is becoming increasingly competitive. To keep up with the escape room market, JOEXAPE hired you to design the locks on the escape room doors. JOEXAPE’s upcoming escape room project has the following theme.

You and your crew have time travelled to Utopian 3026. However, the accent of humans has significantly changed, and humans no longer look the same as humans in 2026. Upon arrival, you and your crew are perceived as a newly discovered species due to differences in accent and appearance and are locked up in a futuristic animal zoo.

The Escape Challenge:

However, the difficulty of the room increases to ensure no animal escapes.

If the password is incorrect, the lock will produce a mild zap, discouraging the animals from interacting with the lock.ELEC2141 – Term 1 2026 – Assignment 1

You are tasked to design an electronic lock where the password and mode can be set by the operator, used in each stage of the escape room. You are also tasked to design a morse code to number decipherer which escape teams will find and use to decipher morse code in the escape event. Finally, you are tasked to design a morse code lock which combines the first two tasks.

Other morse conditions are invalid and can be treated as don’t care conditions.

Task 3: Design a Morse Code Lock

Using task 1 and 2, design a multi-level morse code lock system where the user inputs 20 morse inputs instead of numbers.

MRSIN[19:15] is the most-significant-code and should be matched with SYS4 if ORD = 1.

This continues down to MRSIN[4:0] which is matched to SYS1 if ORD = 1.

You must have three modules named task1, task2 and task3 respectively. You may submit more modules that you use within these modules if you desire, up to a maximum of 10 files.

The task1, task2 and task3 files must have the following port names (if these do not exactly match then your design will fail the autotests):

You must submit the code for all modules (i.e., all .v files) used in your design. Do not submit testbenches.

You can perform a sanity test of your code here: https://forms.gle/Jud5d5efQE9gRXBz8

Tips:

• Consider instantiating modules when writing Verilog.

• There is more than one way to approach the question. It is up to you to justify your design choices. But make sure you are up to date with lecture content so you don’t go down a rabbit hole.