CE339 Assignment 2: VGA Display Design
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CE339 Assignment 2: VGA Display Design
Assignment objectives
This document specifies the second coursework assignment to be submitted by students taking CE339. This assignment is more challenging than the first one and it is meant to provide an opportunity to improve the knowledge of the VHDL language and, more importantly, to design a digital “system”. You will be expected to learn to: a) implement digital system design in VHDL code; b) synthesise and download it to the target hardware; c) test, debug, and verify that the design meets the specifications; d) report about your design.
You are required to design code for your target hardware (a Digilent Basys3 board with a Xilinx FPGA) in order to implement a design that meets the specifications (below). You are required to submit working and correct code and you are strongly encouraged to use a modular coding style (allowing for greater flexibility, maintainability, modularity, and reusability). To show that you master all aspects of the language, your code should prevalently use concurrent statements for combinatorial circuits and sequential code for sequential circuits. Additionally, the use of non- standard packages (e.g. STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED, STD_LOGIC_SIGNED) and BUFFER ports is forbidden, while the use of INOUT ports is accepted only when strictly necessary.
You are supposed to gain familiarity with VHDL coding during the supporting CE339 lectures and through self-study hours, also with the help of the recommended textbooks or any other book about VHDL. You are expected to work on this assignment mostly during lab hours. Your design project should be stored under the GitLab repository that was assigned to you at the beginning of the course. You are supposed to commit often and describe your progress in the commit messages. In order to promote a learning scheme that values the learning process in addition to the submitted final design, your weekly progress (as traced back by the commit logs) will contribute to your assignment mark.
Design specifications
Your task is to write VHDL code to draw the object in figure 1 on a display connected to the VGA port of the Basys3 board. This object consists of a yellow circle and a blue rectangle that overlap. The object is movable, and you must control its movement (up, down, left, and right) using the Basys3 board. The centre button on the Basys3 board should be used to reset the object, and the total number of resets must be shown on the 4-digit 7-segment display.
These specifications should be intended as guidelines and should not constrain you from intro- ducing additional designs, such as better graphics, implementing more realistic physics, randomise the initial position.
Figure 1: Shapes to be drawn on the display.
Report
You should write a report introducing the project and then describing your codings and designs for the assignment. It should first describe the design at a higher level and then detail the implemen- tation of each module in a top-down fashion (rather than in chronological order). Also report if your code worked at the first attempt, what was wrong and how you fixed it. The repository log (if you used it properly) should help you considerably in this task. Your report should also include a discussion of design alternatives that you considered and the motivations for your final choice.
Your document should have a title page and be subdivided into appropriately headed sections. It MUST contain references to the material used in your work (e.g., VHDL code or information available in books or on the Internet). All of the VHDL code submitted should be included in the report in the form of code appendices and be typeset in Courier font (or a suitable fixed- width alternative font of your choice). Your report should be less than 1500 words of narrative (i.e. excluding references, code fragments, pictures, diagrams and schematics). Please write the registration number and word count on the title page of your report.
Submission
Your work must be submitted to the university’s online FASer submission system at the address https://faser.essex.ac.uk/ by the deadline given on the system. No other mode of submission is acceptable. You are strongly advised to upload a draft submission before the last lab hours prior to the deadline, and then update it up to the deadline.
You are required to submit one ZIP archive containing the following files:
1. All source files needed to synthesize your project (but not the temporary files created by Xilinx);
2. A report document submitted in PDF format. DO NOT SUBMIT THIS FILE IN .DOC OR
.DOCX OR SIMILAR FORMATS - SUBMIT PDF.
3. Your repository log in .TXT format.
4. If you want (in your own interest, see next section), submit a .TXT or .PDF file with the transcripts of relevant forum discussions you contributed to.
DO NOT WAIT UNTIL CLOSE TO THE DEADLINE TO MAKE YOUR FIRST SUBMIS- SION. Difficulties with the submission system will not be accepted as an excuse for a missing submission.
Marking criteria
This assignment is worth 25% of the module mark. Marks will be awarded for the VHDL code, including coding style and quality. In addition to the submission, each student will be expected to demonstrate and explain her/his design with confidence and competence during a demo lab session. Marks will be assessed based on:
• Implementation
– Quality of the implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15%
– Modular design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6%
– Generic and re-usable code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6%
– Proper use of comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6%
– Steady progress, adequate use of GIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6%
– Quality and confidence of demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25%
• Report
– Correctness and completeness of report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%
– Clarity of presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%
– Organisation of report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8%
– Quality of diagrams and schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6%
• Others
– Compliance with submission instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2%
Marks below 100% can earn additional credits if the student actively engages in forum discus- sions, asks pertinent questions and gives competent answers to questions raised by classmates.
2026-02-27