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ELEC372/472

INTEGRATED CIRCUITS - CONCEPTS & DESIGN

Assignment 2 – Analogue Design

Declaration of academic integrity

The standard University of Liverpool statement of academic integrity [6] should go here as follows:

By submitting this work electronically, I confirm that I have read and understood the University’s Academic Integrity Policy.

By submitting this work electronically, I confirm that I have acted honestly, ethically and professionally in conduct leading to assessment for the programme of study.

I confirm that I have not copied material from another source nor committed plagiarism nor fabricated, falsified or embellished data when completing the attached piece of work. I confirm that I have not copied material from another source, nor colluded with any other student in the preparation and production of this work.

Section 1: Design and simulation of a CMOS Inverter

a) Set the pMOST with the width (in microns) equal to the number assigned to you (see the list on Canvas). The nMOST should have a width of 4.8 µm.

Paste screenshots of the transient and DC simulations below and discuss overshoot, undershoot, rise- and fall times.

[5/100]

b) Set the widths of both nMOST and pMOST equal to the number assigned to you.

Paste screenshots of the transient and DC simulations below and discuss overshoot, undershoot, rise- and fall times.

[5/100]

c) Set the widths of the nMOST and pMOST devices to be equal to 1.2 µm.

Paste screenshots of the transient and DC simulation below and discuss overshoot, undershoot, rise- and fall times.

[5/100]

d) Set the pMOST to the width assigned to you and design a matched inverter (where rise and fall times are similar) by adjusting the width of the nMOST.

Paste screenshots of the transient and DC simulation below and discuss overshoot, undershoot, rise- and fall times. Discuss how you arrived at the width of the nMOST and how well the design is matching.

[10/100]

e) Discuss the performance of your circuit and how different transistor widths affect it.

[5/100]

f) Sketch a cross-sectional and a top layout view of the CMOS inverter.

[5/100]

g) Explain the physical nature of contact and active area masks and qualitatively how punch-though/DIBL/GIDL are affected by reducing the channel length.

[5/100]

Section 2 - Investigate the power dissipation of a loaded CMOS inverter

a) Discuss briefly how the power measurement circuit works (including a circuit diagram) and you arrived at the values for C and current gain (k) (assuming R = 100MΩ)

[5/100]

b) Plot the total power dissipation, drain current of p-MOST and n-MOST and input and output signal. Discuss your results.

[5/100]

c) Plot the dynamic and short circuit power, show and explain your circuit (include a circuit diagram) and explain your results and discuss how it relates to 2a)

[10/100]

d) Plot the power consumption at a lower frequency and put the results into context to above.

[5/100]

Section 3: Design and investigate the DC and transient response of a 2-input NAND gate by analysis and simulation.

a) The two pMOST widths are to be equal to the number assigned to you and the length of 2.4 µm. The two nMOSTs should have a width of 4.8 µm and a length of 2.4 µm. Perform DC and transient simulations. Look at any internal nodes as well.

[5/100]

b) Investigate the rise/fall times when the width of both pMOSTs and the widths of each nMOST are varied. Document with simulation screenshots and relevant parameters.

[5/100]

c) Repeat the above and adjust the value of the load capacitance C_L to compensate for the different widths of the new transistors. Use your script from assignment 1 to calculate an appropriate load capacitance. Document with simulation screenshots and relevant parameters.

[5/100]

d) Modify the nMOST width to design a ‘matched’ NAND gate. Document with simulation screenshots and relevant parameters. Discuss how you achieved matching.

[5/100]

e) Discuss the performance of your circuit and how different transistor widths affect it.

[5/100]

f) Discuss the influence of the load capacitance on the circuit performance.

[5/100]

g) In assignment 1, you calculated the capacitance of an inverter, and discuss why this model is still appropriate for a NAND gate.

[5/100]