Objectives:

.    To understand the fundamental concepts underlying CMOS gate speed and power performance, as covered in ELEC372/472, in the context of design.

.    To  simulate, verify and investigate CMOS  standard cells using a circuit design package, Multisim.

For guidance, a 15-credit module unit is meant to occupy 150 hours in total (including both private study and contact hours). You should aim to spend about 2-3  hours per week on this assignment.

The remainder of the time will betaken up with background reading and research.

Investigate a range of different transistor widths as indicated below:

a)  pMOST with the width (in microns) equal to the number assigned to you (see the list on Canvas). The nMOST should have a width of 4.8 µm.

b)  Set the widths of both nMOST and pMOST equal to the number assigned to you.

c)   Set the widths of thenMOST and pMOST devices to be equal to 1.2 µm.

d)  Set the pMOST to the width assigned to you and design a matched inverter (where rise and fall times are similar) by adjusting the width of the nMOST. Discuss how you arrived at the

width of thenMOST and how well the design is matching.

e)  Discuss the performance of your circuit and how different transistor widths affect it.

f)   Discuss what the load capacitance stands for.

g)  Sketch a cross-sectional and a top layout view of the CMOS inverter.

h)  Explain the physical nature of the contact and active area masks and qualitatively how punch-

though/DIBL/GIDL are affected by reducing the channel length.

Section 2 - Investigate the power dissipation of a loaded CMOS inverter

a)  Using your ‘matched design’ from section 1d) and calculate a suitable load capacitance using

your script from assignment 1, employ the ‘power meter’ circuit in the MutiSim guidance,

b)  Plot the power dissipation over 5 or more cycles (rise and fall times) of the input signal. Plot input and output voltage waveforms; drain current of p-MOST and n-MOST and power

dissipation of the DUT on the same page but as separate traces.

c)   Devise a simulation that allows separation of dynamic power dissipation and short circuit

current power dissipation.  Comment on the relative magnitudes of the two components.

d)  Repeat the simulation at a lower frequency and compare the results to those of a higher

frequency.

Quote power consumption in both ‘watts’ and as ‘energy per transition’. Check that the values

you are getting are sensible.

Section 3: Design and investigate the DC and transient response of a 2-input NAND gate by analysis and simulation

Design and test (DC and transient responses) a two-input NAND gate as shown in Fig. 2 using the libraries provided with further details below. Use a supply voltage of 5V, an input of 100 MHz 5V clock source and a load capacitance of 20 fF.

Investigate the following conditions:

a)   The two pMOST widths are to be equal to the number assigned to you and the length of 2.4 µm. The two nMOSTs should have a width of 4.8 µm and a length of 2.4 µm. Perform DC

and transient simulations. Look at any internal nodes as well.

b)  Investigate the rise/fall times when the width of both pMOSTs and the widths of each nMOST are varied.

c)   Repeat the above and adjust the value of the load capacitance CL  to  compensate for the different widths of the new transistors. Use your script from assignment 1 to calculate an appropriate load capacitance.

d)  Modify thenMOST width to design a ‘matched’ NAND gate.

e)  Discuss the performance of your circuit and how different transistor widths affect it.

f)   Discuss the influence of the load capacitance on the circuit.

g)  In assignment 1, you calculated the capacitance of an inverter, and discuss why this model is still appropriate for aNAND gate.