Deliverables:

●    List of team members (you may name your team)q

●   A HERA program demonstrating double-precision work via

○   Code that uses standard HERA operations to find Fibonacci(n) for n up to 47

■   This will involve using double-precision idioms

■    Include a comment giving the value and number of clock cycles needed to compute Fib(5), Fib(6), Fib(7), Fib(24), and Fib(25).

○   A test suite for your double-precision hardware instructions

○   Code that uses the newly-introduced double-precision HERA operations to find Fibonacci(n) for n up to 47

■   Once again, include a comment giving the results and clock cycles needed to compute Fib(5), Fib(6), Fib(7), Fib(24), and Fib(25).

●    Hardware for double-precision processing

○   HERA_CPU_DMATH folder with the circuits for double-precision ADD (DADD) and SUB (DSUB)

■    Ideally, the instruction ROM should contain a small but representative test case initially

○    Be sure to place the names of your team and team members as a text comment at the main level of your team’s main  .circ.

○   A supporting document HERA_CPU_DMATH.pdf with technical details (i.e., how to open and run your circuit and where to place input/read output) -- screenshots  may help.

Lab Work:

Double-Precision Coding without Hardware Modifications

Write a program to find Fibonacci(n) for n up to 47. You may assume your parameter n starts in R1; put the result in R3 (most-significant 16 bits) and R2 (least-significant bits).

Test your program on your HERA CPU from Lab 1H (you may choose the result from any

member of the team, or the one in the starter files for Lab 2H), and confirm that you get 5 for Fib(5) and 144 for Fib(12).

Figure out how many clock cycles are needed to find Fib(5), Fib(6), Fib(7), Fib(12), Fib(24), and Fib(25), and add a comment to your program giving the six values and the number of cycles

needed for each. Please show your work for how you counted cycles … you may either add

elements to your HERA circuit to count the number of (non-HALT) clock cycles, starting from 0 when the chip is reset; or, you may analyze the number of steps by hand (be careful; remember that LABEL doesn't take any time, and SET takes 2 clock cycles, since SETLO and SETHI each take 1).

Extending the HERA Architecture for Double Precision ADD/SUB

We will be using the following definitions for double-precision addition and subtraction in HERA:

●   DADD(d, a, b)         0010 1010 00dd aabb

●   DSUB(d, a, b)         0010 1011 00dd aabb

Where dd, aa, and bb are two-bit designations for register pairs using the following conventions:

The rules for flags with DADD and DSUB should be extensions of the ADD and SUB rules, i.e., the same rules from Section 2.2/Page 14, but with 16 more bits. So, instead of the sign-flag (s) rule being to have the CPU "... set s, to b 15  of the result", you would "... set s, to b 31  of the

result".

Before making significant use of your new hardware (or, preferably, before even building it),

write some tests, exploring simple/obvious cases, as well as interesting "corner cases". Check   each result (using standard HERA instructions) and HALT if there is an error before the test is    complete. Once you've got the hardware built, run the tests and debug your hardware; keep the tests and submit them with your lab work.

To get started, make a copy of the HERA.circ starting file; name the copy HERA_DP.circ  which will hold the revised circuit.  Consider how the HERA processor cycle determines which instruction is executed.

Expect most of the work to occur in the Register File which is found in the module

“ RegsiterBank” you will work in the file “ RegisterBank.circ” to revise the register file, save work, then run “main” in the file “ MainHERA.circ” .

your new module to perform double-precision arithmetic should be in the file “ALSU.circ” .  We     suggest a new module/circuit in the module “ALSU” (since the existing ALSU_body will not have enough input/output for double precision).

In particular, you will need to review how registers are read and written, especially written

concurrently.  You will need to add more output and inputs (or perhaps repurpose some of the existing inputs/outputs.  This will likely involve replacing the Register File circuit.

All flags would need to be read and updated depending on the double-precision value resulting from this operation.

Remember to commit each step of your work, and run your tests, debug, and edit as needed. Commit and push, once you're done; talk to Dave if you want a shared git repository to

coordinate work within your team. If you do this, avoid situations in which different people are

editing the same file at the same time! The goal is to ensure that nobody is ever editing a file for which someone else has un-pushed changes.

Double-Precision Coding with Hardware Modifications

Write a program to find Fibonacci(n) for n up to 47 by using your new DADD instruction to add elements of the sequence. As with your previous function, you may assume your parameter n starts in R1; put the result in R3 (most-significant 16 bits) and R2 (least-significant 16 bits).

Test your program on your extended HERA CPU, since you can't run it on HERA-C or HERA-py, and confirm that you get the right answers to the examples you ran with your single-precision

program above, i.e., Fib(5), Fib(6), Fib(7), Fib(12), Fib(24), and Fib(25),

Figure out how many clock cycles are needed to find Fib(5), Fib(6), Fib(7), Fib(12), Fib(24), and Fib(25), and add a comment to your program giving the six values and the number of cycles

needed for each. If you analyze the number of steps by hand, show your work (the same

hardware cycle-counter will work for both questions about counting, you don't need to build a second copy).

Double Precision Example

Given 6400010  = FA0016 , then 64000 + 64001 = 128001 which is greater than 216  = 65536. Thus, we would get carry when (16-bit) single-precision addition, but we should be able to handle this  operation in (32-bit) double-precision.

Consider the use of our DADD instruction to add 0xFA00, which we assume is placed into [R7 R6], and 0xFA01, assumed in [R9 R8]. We could write this as DADD(01, 10, 11) in our

"extended" HERA; the binary for this instruction would be 0x2a1b:

DADD(01, 10, 11) ⇒ 0010  1010 0001 1011  [⇒ 2a1b in HEX]

Let's consider what happens when we execute that instruction, assuming that carry is True and not blocked, i.e., if we had CCBOFF( )  CON( ) DADD(01, 10, 11).

Note that the carry-out will be False, since there was no need to carry out of that leftmost place.

Note that the DADD/DSUB instructions will not work in the standard HERA tools such as

HERA-C or HERA-py simulator; your job will be to make them work in the hardware. You can enter them in the Hassem assembler via, e.g., OPCODE(0x2a1b).1

Rubric (tentative)