Digital System Design Fall 2023 Homework Assignment 3
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Fall 2023 Digital System Design
Homework Assignment 3
Due date: Dec 18 Monday
Problem 1 (Carry Lookahead/Selector Adder Design, Mandatory)
Use Verilog to design and implement an 8‐bit Carry Lookahead Adder OR 8‐bit Carry Selector Adder. You can choose to either use or not use generate statements.
Materials to be submitted:
1. Verilog codes for carry lookahead/carry selector adder module.
2. Verilog codes for testbench.
3. Image of the screen that shows the test results.
Problem 2 (Carry Skip Adder Design, Optional)
Use Verilog to design and implement a 16‐bit Carry Skip Adder. You can choose to either use or not use generate statements.
Materials to be submitted:
1. Verilog codes for carry skip adder module.
2. Verilog codes for testbench.
3. Image of the screen that shows the test results.
2023-12-06