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EE515 - Continuous Assessment/Assignment_2

2023

For this assessment, you are tasked with reducing the delays, in a pipelined circuit, through retiming.

Consider the Data Flow Graph (DFG) below.

Assuming that the multiplication takes 2 time units and the addition takes 1 time unit,

•    identify the loops

•   The iteration period bound (IPB)

•   calculate the critical path

•   draw a retimed diagram to reduce the critical path delay.

Benefits as an Assessment

The main objective of this assignment is to give the student much deeper understanding of Synchronous  Digital Systems. Specifically, this  assessment will furnish the student with a comprehensive knowledge on combinational clouds, propagation delays, latency, critical path andretiming techniques.

The assessment will require independent study and problem-solving skills. Aspects provided in the module will provide the scaffolding needed to complement the self-learning.

Marking Scheme

A detailed marking scheme would be used to grade the submissions.

Guidelines

•   Only PDF files will be accepted!

•   A submission portal will be opened prior to the deadline.

•    Please note that diagrams are critical. Each and every step of the retiming should be drawn and explained using bullet points.

STRICT DEADLINE: 29th of November 2023 – 11 pm-Irish time.