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FINAL EXAMINATION

Term 3, 2022

ELEC4602

Microelectronics Design and Technology

QUESTION 1 [25 marks]

Figure 1 shows a layout implemented in the 45 nm CMOS process described in the information sheet (n+implant and p+implant layers not shown). Process parameters, device equations, layer key and design rules can be found on the information sheet.

Figure 1: Circuit layout. Drawn to scale.

(A) Draw the x-x 0 cross section.

(B) Draw the circuit schematic of the layout, including transistor dimensions and types, and mark the nodes A to D on the schematic.

In the following, it is assumed that node B is the negative suppy voltage and node D is the positive supply voltage.

(C) Show how to add suitable well contacts(s) to the layout, including the n+implant and p+implant layers.

In the following, it is assumed that the POLY sheet resistivity is R = 8Ω/ and that the field POLY-POLY minimum distance is 140 nm. A POLY resistor, R must be placed in an area of 10µm×10µm.

(D) Estimate the largest value R can have.

A tape-out check-list includes the following three items:

1) Design Rule Check (DRC),

2) Layer-Vs-Schematic check (LVS) and

3) corner simulations.

(E) For each of the three items, explain what the possible consequences of not doing the item before tape-out would likely be.

QUESTION 2 [25 marks]

Figure 2(a) shows a variable-gain amplifier implemented in the 45 nm CMOS process described in the information sheet. The amplifier uses an ideal op-amp powered from a single supply (VDD = 0.9V) and a 5-bit digital potentiometer (digipot) which is implemented as shown in Figure 2(b). Key circuit parameters are shown in Figure 2(c). Bulk effect and, where appropriate, channel length modulation can be ignored in this question.

Figure 2: Variable-gain amplifier (a). Digital potentiometer (b). Key circuit parameters (c).

The digipot is controlled by a 5-bit digital word X (0 ≤ X ≤ 31) such that the switch control signals are xX = 1 and xn = 0,n = X. Logic high levels used are VDD (1) and 0V (0). Low VT transistors are used for the digipot switches which must have gate overdrive (effective) voltages of at least Veff,min = 0.15V. The resistance between the digipot A and W terminals are denoted RAW and the (small signal) switch on-resistance denoted rS. (Note: currents in the switches are small).

(A) Find the maximum small-signal on-resistance of the digpot switches, rS,max.

(B) Find RAW expressed in X, RU and rS.

In the following, it is assumed the op-amp input capacitance is Cin = 50 fF, that switch capaci-tances can be ignored and that rS = 2.5 kΩ. Cin in conjunction with the digipot resistances forms an extra pole in the feed-back loop at a frequency fSC which depends on X.

(C) Find lowest value for fSC(X), fSC,min.

In the following, it is assumed that the maximum output voltage of the op-amp is vOut,max =VDD. To ensure Veff ≥ Veff,min, a maximum voltage on the op-amp negative input (ie. the digipot W terminal) must be imposed, inferring a maximum allowed value for X, Xmax.

(D) Find Xmax.

The voltage requirement on the digipot limits its general use. The design can be modified such that there is no restriction on digipot terminal voltages (other than being within the supply rails).

(E) Modify the digipot design to remove terminal voltage restrictions.

QUESTION 3 [25 marks]

An 8-way one-hot decoder is to be designed in the 45 nm CMOS process described in the infor-mation sheet. This combinational decoder must have a 3-bit control signal Z = b2b1b0 (0 ≤ Z ≤ 7, b2 most significant bit) and 8 outputs (z0 to z7) where zZ = 1 and zn = 0,n = Z. Figure 3 shows a decoder unit which can be used to build this decoder. Regular VT devices are used in this design and the power supply voltage VDD = 0.9V. Simplified digital transistor models may be used in this question.

Figure 3: One-hot encoder unit.

It is assumed that the output X load capacitance is small.

(A) Choose transistor dimensions for M1–M4 and argue for your choice.

In the following, it is assumed that dimensions for all transistors in the design are W = 120 nm and L = 60 nm. Further, it is assumed that the external load capacitance on node Y is CLY = 1 fF.

(B) Find the S-Y rising propagation delay, tSY,LH

In the following, it is assumed that power dissipation in the decoder is due only to switched capacitance; ie. leakage and crow-bar currents can be ignored. Over Process, Voltage and Tem-perature (PVT), the supply voltage varies by ∆VDD/VDD = ±5%, resistances (including transis-tor on-resistances) vary by ∆R/R = ±15%, and capacitances (including transistor capacitances) vary by ∆C/C = ±10%. All variations are from nominal values and are assumed independent. Assuming the decoder operates at a set frequency, its power draw will vary over PVT.

(C) Find how much the decoder power draw might deviate from its nominal value over PVT.

(D) Design the 8-way one-hot decoder.

In the decoder unit’s circuit calculating X, the S and B inputs could be swapped achieving the same logic function. Similarly for the circuit calculating Y.

(E) Explain why neither of these alternatives were used.