Exercise 1: expected time, 1.5 hour

Behavioral design is especially well suited to sequential circuits, and in this exercise will introduce the behavioral design of a D-type flip-flop (DFF) and a 4-bit register that instantiates DFF modules.

Task A: Time to get sequential!

1.   Building on the skills in behavioral circuit design you established in DP1-2 (and referring back to those Manual sections and Tutorial as needed), in Vivado, create a new module called DFFr

containing a behavioral description of a positive (rising) edge triggered D-type FF with an  asynchronous active-high reset (rst) input. The module should have inputs: d, clk, rst; and outputs: q, qbar.

Hint: An asynchronous reset means one that will force the output to 0 (or possibly some other   fixed value, but normally 0) without waiting for a clock edge trigger. In behavioral design, this is straightforward to implement using an if-then test of the reset signal that acts with priority over  other, normal (non-reset) circuit functionality.

2.   Use the DFFr behavioral skeleton (i.e., incomplete!) code below to implement the DFFr module design.

module DFFr( );

input , ,  ;

output reg ;

always @ (posedge(clk), posedge(rst))

begin

if (expression)  inputX =  value;

else  inputX = value ;

end

endmodule

3.  When the design module is complete, open the DP_Manual to section 3.8. Simulation Signal Timing and read this section to help you write testbench simulation signals for synchronous

sequential circuits. Answer the question about this DP_Manual section in the Worksheet.

4.   Build a testbench and verify the DFFr operation for each of the following actions:

a.   output (q) 0  1 on triggering clock edge

b.   output (q) 1  0 on triggering clock edge

c.   output (q) 1  0 when rst  1 (not synchronized to clock edge), and

i.   while rst=1, q stays 0

ii.   when rst  0, q again followed behavior in a) and b)

5.   Once your DFFr module has been functionally verified, in your Worksheet, paste a copy of your final DFFr module Verilog code, your final DFFr testbench module code, a screenshot of the

simulation waveforms, and provide a description of how these waveforms verify the “actions” listed in the previous step.

Task B: Multi-bit me

6.   In Vivado, create a new module called 4bReg containing a behavioral description of a 4-bit register with synchronous load (ld) and an asynchronous reset (rst) control inputs following these guidelines:

a.   the 4-bit data input and 4-bit data output should be implemented as vectors: D[3:0], Q[3:0]; note, 4bReg will only have a Q output and qbar of DFFr will be unused

b.   the asynchronous reset should use the reset built into the DFFr cell (just wire all DFFr/rst inputs to a single 4bRed/rst input

c.   the synchronous load input should, on triggering clock edge, either load in a new value (when ld=1, Q=D) or hold the prior value (when ld=0, Q=Qprevious); structurally this

would be implemented with a 2:1MUX at the data input to each DFFr module, but you need to determine how to implement this behaviorally.

7.   Build a testbench module for 4bReg and verify its operation for each of the following actions:

a.  when ld=1, Q  D on triggering clock edge; verify for two 4-bit values of D

b.  when ld=0, Q holds value through triggering clock edge; verify for two 4-bit values of Q

c.   output (Q) x  0 when rst  1 (not synchronized to clock edge), and

i.   while rst=1, Q stays 0

ii.   when rst  0, Q again followed behavior in a) and b)

8.   Once your 4bReg module has been functionally verified, in your Worksheet, paste a copy of

your final 4bReg module Verilog code, your final 4bReg testbench module code, a screenshot of the simulation waveforms, and provide a description of how these waveforms verify the “actions” listed in the previous step.

Exercise 2: expected time, 1.5 hour

In this exercise, we’ll expand our understanding of sequential circuits while creating and simulating a counter module.

Task A: Defining an n-bit counter

1.   Review the n-bit down-counting counter circuit description below and answer related questions in the Worksheet to demonstrate your understanding of this circuit.

•    inputs

o clk: a free-running (constant frequency, not gated or blocked) 100MHz square wave

o cnt: active-high “count” control signal that enables down-counting; if cnt = 0, the counter will be in hold mode and will not count down

o load: active-high control signal that activates loading a start value into the counter register; load should override (have priority over) the cnt signal

o rst: active-low “reset” control signal that forces the counter output, cout, to 0; rst should override (have priority over) both cnt and load signals

o start: (an n-bit vector) the n-bit counter start value that will be loaded into the counter register when the load signal is active; when the counter output, cout, reaches 0, it

will wrap back to start on the next clock cycle

•    outputs

o cout: (an n-bit vector) the n-bit counter output containing the current counter value

o wrap: a signal that will idle at low/0 and pulse to high/1 when counter output, cout, reaches 0 and then return to 1 when the counter wraps back to the start value

•    program constant

o program constants define parameters that are coded as variables within the circuit module and assigned a constant value within the Verilog code to simplify

configuration of the module by redefining the constant value

o our counter will be defined using a program constant width that defines how many bits wide the counter is; e.g., width = 8 will generate an 8-bit counter

•    operation

o the counter circuit inputs should initialize to cnt = load = rst = 0 and start = “max counter value” (a function of the counter width)

o counter output, cout, is determined by which mode the counter is in, and control

signals implement these modes: reset (cout=0), load (cout=start), hold (cout=cout), count (cout=cout- 1)

. counter circuit is defined to create these mode priorities: reset (highest), load, hold, count (lowest)

o when down-counting counter output, cout, reaches 0, warp  1, and on next clk trigger cout  start and wrap returns to 0

In this exercise, you will be provided with fully functional counter circuit and testbench code, and   then you will explore the design by studying and explain the simulation results and then modifying the design as directed below.

Task B: Implementing an n-bit counter

2.   In Vivado, create a new module called counter and paste in the fully-functional counter module Verilog code shown in Appendix A (and provided as a separate .txt file) . The provided code

should completely replace any auto generated code in this file.

3.   Save the design module, then study the code and answer the related questions in the Worksheet.

4.   Create a testbench module called counter_tb and paste in the fully-functional testbench module Verilog code shown in Appendix B (and provided as a separate .txt file).

5.   Save the testbench. If necessary, set this testbench to Top and close any prior simulations. Then, Run Behavioral Simulation and open the resulting waveforms.

6.   In the simulation waveforms panel, make the following adjustments

•    Remove the WIDTH parameter; it is a program constant that is not needed to verify   circuit behavior. To do this, right click on the WIDTH signal name and select “cut” (or “delete”).

•    Click-and-hold on the START signal and drag it to the top of the signal list. This signal only changes value once and is less vital to verifying functionality. Also, doing this will show you that signals can be moved around.

•    Highlight the output signal vector COUT and setting it to a different color of your choice. Then set WRAP to another color of your choice.

•    Scale the waveform window (or possibly the overall Vivado window) to both 1) show all 400ns of the simulation and 2) ensure the COUT value can be each in each counting

step.

•    Right-click on the COUT signal, select Radix, and set to Unsigned Decimal. Observe the change to the COUT signal. Then change it back to display in Hexadecimal.

7.   Take a snapshot of the simulation waveforms (cropped to show all signal names and all waveforms from 0 – 400ns) and paste it in the Worksheet.

8.   Study the simulation waveforms, the design module code, the testbench code, and the

comments in both code files to figure out what is going on in this circuit and this simulation.

When you are confident you know how the circuit works and how the simulations demonstrate all operations modes (and some repeated modes), answer the related questions in the

Worksheet.

Next you will get a chance to prove you understand the counter circuit and the provided Verilog module description and testbench by modifying the design and testing the modifications.

Task C: Modifying counter Design

9.   Modify the counter module so that the reset signal, rst, is asynchronous and will initiate a reset immediately without waiting for a clock trigger.

10. Without modifying the testbench, simulate the modified circuit, organize your waveforms, paste a snapshot in the Worksheet and describe how the results are different from before and how

these waveforms verify rst is operating asynchronously. You may need to compare to the prior waveforms to explain the difference.

11. Modify the width (design module) and WIDTH (testbench) parameter to create a 16-bit counter, and modify the testbench to load a start value of 0x0E08 (rather than 5) using Verilog hex

notation.

There is likely a way we could specify the “width” only in the design module and have that

parameter pass into the testbench, but that requires some Verilog trickery beyond the scope of this project.

12. Simulate the modified circuit and organize the waveforms. Observe the overall operation of the 16-bit counter and answer the related questions in the Worksheet.

You should notice you have to zoom in more to see the 16-bit counter value within the COUT waveform than you did with the 4-bit version.

13. In the waveform plots, zoom into the section where the new START value (0x0E08) is loaded    and scale the plots so you can see ~100nsec around where LOAD is high. Paste a snapshot of this view in the Worksheet and answer the related questions.

14. Choose some other unexplored feature/operation of the counter and edit the module and/or

testbench code to modify that operation (you pick what to change!). Then, in the Worksheet

describe what behavior you wanted to change, how you changed it, and what differences

resulted in the simulation results. Include a snapshot of simulation waveforms if useful to explain the results of your modification(s).

Try to think of something on your own, something unique to you. If you really can’t find anything to modify, try changing (or adding to) the testbench to show what would happen if two control

signals were activated at the sametime (like load=1 and cnt=0, or some other combination of your choosing). For this, you should be able to observe which mode the counter enters and

explain how you can tell this from the simulations.

Exercise 3: expected time, 1.5 hour

Task B: Code it up!

4.   Launch Vivado and create a new module named traffic. Following the 5-section FSM Verilog   code structure detailed in the FSM-Verilog-Guide, and using the FSM code example in slide 6 as a reference, implement your traffic light state diagram in Verilog. All of the state, input, and   output signals for this FSM are defined in the description from step 1. Here are a few addition   hints:

•    This FSM has 4 states, so you’ll need a 2-bit current state variable (like curst or state in the guide). You will also need to declare a 2-bit next state variable (like nxtstor next).

•    This FSM has 2 inputs signals with different functionalities for different states. We have not defined a reset (rst) signal shown in some of the guide examples, so omit reset.

•    This FSM has 3 outputs (lights), and all outputs should be clearly defined for all states.

The FSM-Verilog-Guide file was designed to help you through this initial FSM design, so put it to use as you code this FSM module. The next/final DP will be a complex open-ended FSM

design project where all you will be given is a real-world behavior description like that in step 1. So, do your future self a favor by learning the basic FSM design process now.

5.  When you are done with the FSM design coding, save the design module. This would be a good time to ask a friend who is in this class or has had this class recently to give you feedback on

your FSM code. Or, stop by office/help hours and get some feedback.

Task C: Simulation and Verification

6.   Create a testbench module called traffic_tb and used paste testbench examples to create the testbench module with the following hints/suggestions:

Define the testbench module signals and instantiate the traffic module like normal.

Initialize the clk, pow, and str signals to 0.

Create a free running clk signal with 10nsec period, where we will assume the simulated

10nsec represents the 10sec desired timing cycle of the traffic light (it is a bit complicated to get the simulator to work in seconds scale).

You can create your own input test sequence or use the one below and then figure out what is it doing/testing.

initial begin

#20 POW = 1; //turn on

#50 STR = 1;  //begin next light cycle

#10 STR = 0; //reset start signal

#50 STR = 1; //check another light cycle

#10 STR = 0; //reset start signal

#10 POW = 0; //test power down

#20 POW = 1; //test start after power down

#40 POW = 0; //test power down from different state #20 POW = 1;

end

initial #300 $finish;

7.   Save the testbench. If necessary, set this testbench to Top and close any prior simulations. Then, Run Behavioral Simulation and open the resulting waveforms.

8.   In the simulation waveforms panel, make the following adjustments

•    Arrange the inputs to the top of the waveforms and put the light outputs (g, y, r) beneath them, ideally in a sequence that helps you understand and debug your design.

•    Set some distinctive colors for signals to help you understand and debug your design.

Note, at the time of this writing, our simulations of the traffic module are resulting in correct light outputs and proper response to pow and str inputs; however, the state variables are showing X  value for any non-zero state (despite the fact that the FSM is clearly going through all states to    set the proper outputs). We’ve yet to trackdown why this is happening. ☹

9.   If your simulations do not look correct, debug the design module and testbench and simulate until everything is working like the state diagram suggests.

10. When your design is complete, working as expected and fully verified, in your Worksheet, paste a copy of your final traffic module Verilog FSM code, your final traffic testbench module code, a  snapshot of the simulation waveforms, and provide a description of how these waveforms verify proper FSM operation.

That completes the experimental portion of Design Project 3 wherein you have demonstrated skills with several important elements of Verilog HDL digital design.

Discussion Topics: expected time, 0.5 hours

The last step of DP2 is to write responses for the Discussion Topics in the  Worksheet. Discussion Topic

responses are 33% of your DP grade and should be answered in short paragraphs with complete sentences following English grammar rules and using professional language.

Appendix A: counter module code

Fully functional n-bit counter module in behavioral Verilog.

`timescale 1ns / 1ps

//ECE230 DP3 Ex2 Provided Counter Code

//ver: Nov11,2023, by DRAM

module counter

#( parameter integer width = 4 )   //parameter 'width'defines how many bits the counter contains

(

input clk, cnt, load, rst,

input [width- 1:0] start,

output reg [width- 1:0] cout,

output reg wrap

);

always @ (negedge clk) begin

//nested if-else block to set counter mode

if (!rst) cout = 0;                 //reset mode

else if (load) cout = start;    //load mode

else if (!cnt) cout = cout; //hold mode

else if (cout) cout = cout - 1;  //count mode, count down

else cout = start;          //count mode, wrap to start

//if-else block to toggle wrap when cout=0

if (!cout) wrap = 1;

else wrap = 0;

end

endmodule