ELEC 212 CMOS INTEGRATED CIRCUITS SECOND SEMESTER EXAMINATIONS 2017/18
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ELEC 212
SECOND SEMESTER EXAMINATIONS 2017/18
CMOS INTEGRATED CIRCUITS
1. a) Explain with a short statement, the difference between intrinsic and extrinsic semiconductors.
b) Derive and illustrate with the aid of a diagram, the kinetic energy versus wavevector for a free electron.
c) State the mass-action law for semiconductors and explain the significance of each term.
d) The conductivity of extrinsic n-type silicon is designed to be 300 (Ωm)- 1.
The mobility of electrons is 0.1 m2 / Vs.
i) Calculate the doping concentration of extrinsic dopant ions to satisfy this requirement.
ii) State one possible dopant for n-type semiconductor.
iii) Calculate the position of the Fermi level (in eV) from the conduction band edge for the semiconductor in i).
e) Explain the surface field effect and draw the energy band diagram for a Metal Oxide Semiconductor (MOS) capacitor in inversion.
f) The MOS capacitor is designed to have a threshold voltage, VT = 0.9 V. Calculate the gate oxide thickness for the MOS capacitor to satisfy the required threshold voltage. The doping concentration of ann-type substrate
is 5 根 1022 m-3. Assume an ideal MOS capacitor.
Total 40
2. a) Develop an expression for the current flowing in the channel of an n-MOSFET in terms of the gate (VG), drain (VD) and threshold (VT) voltages, in the linear region:
ID = μCo 
[(VG VT )VD 
] .
b) Define the device constant in the equation in a). What parameters can the designer vary and why?
c) The n-MOSFET in a) is used to fabricate a complementary metal oxide semiconductor (CMOS) inverter. Design its aspect ratio (W/L)n to obtain a
symmetric CMOS inverter. Themobilities of electrons and holes are
μn = 545 cm2/Vs and μp = 130 cm2/Vs respectively, the threshold voltages for p- and n-MOSFETs equal to VTn = |VTp | = 0.7 V, VDD = 5 V, and the aspect
ratio for the p-MOSFET (W/L)p = 6.
d) Sketch the transfer characteristic of aCMOS inverter and illustrate the regimes of operation, referring ton- and p-MOSFET transistors.
Total 30
3. a) Draw the circuit diagram of a two-input NOR gate, fabricated in CMOS technology. Describe the principles involved in its design.
b) Two-input NOR and two-input NAND gates are to be designed using a process technology with the gate length L = 0.5 μm. The aspect ratio (W/L) of a minimum-size symmetric inverter is W/L = 1.75.
i) What is the width (W) and length (L) of n- and p-MOSFETs and their aspect ratios (W/L) required in the design?
ii) Comment on the issues concerning the use of NOR versus NAND gates in CMOS integrated circuit design.
c) Draw the voltage transfer characteristics of a pseudo CMOS inverter and state its key disadvantage in comparison to a CMOS inverter.
i) What kind of applications is a pseudo-nMOS inverter suited for?
d) Illustrate a two single-input domino CMOS logic gate connected in cascade and draw the voltage waveforms during the evaluation phase. Explain briefly its operation.
Total 30
2023-09-04