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ELEC 212

SECOND SEMESTER EXAMINATIONS 2022-23

CMOS INTEGRATED CIRCUITS

Answer ALL three questions.

Additional Information:

Constants:

q = 1.6 × 10- 19 C

k = 1.38 × 10-23 J/K (Boltzmann’s constant)

T = 300 K (room temperature)

ni = 1.45 × 1016 m-3 (intrinsic carrier concentration of silicon at 300 K)

εs = 11.9 (the relative permittivity of Si)

εox = 3.9 (the relative permittivity of SiO2)

ε0 = 8.85 × 10- 12 F/m (the permittivity of vacuum)

Eg = 1.12 eV (band gap of silicon semiconductor)

1.   a)    The De Broglie hypothesis implies the wave-particle duality for an electron. State this relation and explain the significance of each term.     5

b)   Derive and illustrate with the aid of a diagram, the kinetic energy versus wave vector for a free electron.     5

c)    Explain the terms:

(i)        direct semiconductor     3

(ii)       indirect semiconductor.     3

State at least one semiconductor for each type above.     2

d)   The doping concentrations of p-  and n-type silicon are 3´ 1017  cm-3  and 2´ 1016 cm-3 respectively. Assume a temperature of 300 K.

i)         Calculate values of the Fermi potential for p- and n-type silicon.     4

ii)        Calculate  the  built-in potential  for  a pn-junction fabricated from these p- and n-type semiconductors.      4

iii)       Calculate the depletion width for the pn-junction in ii).     6

iv)       If the pn-junction  is to be  designed  so that its depletion width is entirely on the p-type side of the junction, comment on how the doping concentrations above need to be changed.      3

e)    Draw an energy band diagram for the pn junction in d) under the zero bias condition. Label the band edges, the extrinsic and intrinsic Fermi levels.          5

Total

40

2.   a)    Develop an expression for the current flowing down the channel of an n-MOSFET in terms of the gate (VG) and threshold (VT) voltages, in the saturation region (above ‘pinch off’):                     10

W               2

ID  = µCo  2L (VG  - VT )

Assume the drain current equation in the linear region as a starting point in deriving the above equation.

b)   Define the device constant in the equation in (a). What parameters can the designer vary and why?           2

c)    Consider enhancement and depletion types of n-MOSFETs.

ii)        State the key difference between these two types of n-MOSFETs.            2

d)   You   are   asked   to   design   a    symmetric   complementary   metal   oxide semiconductor (CMOS) inverter.

Assume the mobilities of electrons and holes are µn  = 545 cm2 / Vs and µp = 130 cm2 / Vs respectively, the threshold voltages for p- and n-MOSFETs equal, VTn  = |VTp | = 0.7 V, VDD  = 5 V, and aspect ratio for the p-MOSFET (W/L)p  = 8.

i)         What is the minimum aspect ratio (W/L)n   for an n-MOSFET which would meet this requirement?   8

ii)        Is the CMOS inverter a ratioless or ratioed logic circuit? Explain your reasoning with the aid of diagrams.    4

Total

30

3.   a)    Draw a plan view (layout) of a CMOS inverter including polysilicon and  aluminium lines, contacts and implants.         4

b)    State the two most important masks used in a CMOS design layout.                        2

c)    Consider a 2-input CMOS NAND logic gate.

i) Draw the circuit and label clearly the inputs, the output, the supply voltage (VDD), ground, n-MOSFETs and p-MOSFETs.    3

ii) Explain briefly how the circuit works and state the truth table.      3

iii) Describe the principles involved in the design of this logic gate.        6

d)   You are asked to design two-input NOR and two-input NAND gates for a process technology with the gate length L = 0.5 µm. The aspect ratio (W/L) of a minimum-size symmetric inverter is W/L = 1.75.

i)         What is the width (W) and length (L) of n- and p-MOSFETs used in  the design?           8

ii)        Comment  on the  issues concerning the use of NOR versus NAND gates in CMOS integrated circuit design and state which would be the preferred choice.          4

Total

30