ELEC 212 CMOS INTEGRATED CIRCUITS SECOND SEMESTER EXAMINATIONS 2021-22
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ELEC 212
SECOND SEMESTER EXAMINATIONS 2021-22
CMOS INTEGRATED CIRCUITS
Answer ALL three questions.
The use of a calculator IS allowed.
Additional Information:
q = 1.6 根 10- 19 C
k = 1.38 根 10-23 J/K (Boltzmann’s constant)
T = 300 K (room temperature)
ni = 1.45 根 1016 m-3 (intrinsic carrier concentration of silicon at 300 K)
εs = 11.9 (the relative permittivity of Si)
εox = 3.9 (the relative permittivity of SiO2)
ε0 = 8.85 x 10- 12 F/m (the permittivity of vacuum)
Eg = 1.12 eV (band gap of silicon semiconductor)
1. a) Describe the meaning of ‘direct ’ and ‘indirect ’ semiconductors. State the typical semiconductors that belong to each group. 6
b) Derive and illustrate with the aid of a diagram, the kinetic energy versus wavevector for a free electron. 7
c) State the mass-action law for semiconductors and explain the significance of each term. 5
d) The conductivity of extrinsic p-type silicon is designed to be 150 (am)- 1.
The mobility of holes is 0.05 m2 / Vs.
i) Calculate the doping concentration of extrinsic dopant ions to satisfy this requirement. 4
ii) State one possible dopant for p-type semiconductor. 1
iii) Calculate the position of the Fermi level (in eV) from the valence band edge for the semiconductor in i). 4
e) Describe what needs to be added to the p-type silicon semiconductor in d) to fabricate a MOS capacitor. Explain the surface field effect. 5
f) The MOS capacitor is designed to have a threshold voltage, VT = 0.8 V.
Calculate the gate oxide thickness for the MOS capacitor to satisfy the required threshold voltage. The doping concentration of a p-type substrate is 2 根 1022 m-3. Assume an ideal MOS capacitor. 8
Total
40
2. a) Develop an expression for the current flowing in the channel of an n-MOSFET in terms of the gate (VG), drain (VD) and threshold (VT) voltages, in the linear region: 10
ID = μCo [(VG VT )VD ] ,
where the symbols have their usual meanings.
b) Define the device constant in the equation in a). What parameters can the designer vary and why? 3
c) State the difference between the enhancement and the depletion types of MOSFET. Sketch the symbols and transfer characteristics of these two types of devices for p- and n-channel transistors. 5
d) The n-MOSFET in a) is used to fabricate a complementary metal oxide semiconductor (CMOS) inverter. Design its aspect ratio (W/L)n to obtain a symmetric CMOS inverter. Themobilities of electrons and holes are μn = 545 cm2/Vs and μp = 130 cm2/Vs respectively, the threshold voltages for p- and n-MOSFETs equal to VTn = |VTp | = 0.8 V, VDD = 4 V, and the aspect ratio for p-MOSFET (W/L)p = 8. 10
e) State the two key parameters, which govern the speed of CMOS inverters. 2
Total
30
3. a) Explain briefly the operation of a CMOS inverter. State its main advantages and disadvantages. 6
b) Sketch the transfer characteristic of aCMOS inverter and illustrate the regimes of operation of referring n- and p-MOSFET transistors. 4
c) Draw the circuit diagram of a two-input NOR gate, fabricated in CMOS technology. Describe the principles involved in its design. 8
d) Two-input NOR and two-input NAND gates are to be designed for a process technology with the gate length L = 0.5 μm. The aspect ratio (W/L) of a minimum-size symmetric inverter is W/L = 2.
i) What is the width/length (W/L) of n- and p-MOSFETs required in the design? 8
ii) Comment on the issues concerning the use of NOR versus NAND gates in CMOS integrated circuit design. 4
Total
30
2023-08-23