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ELEC 212

SECOND SEMESTER EXAMINATIONS 2020-21

CMOS INTEGRATED CIRCUITS

Answer ALL three questions.

1.   a)    Describe  with  two  brief  statements  the  meaning  of  ‘p’  and   ‘n’  type semiconductors. 2

b)    State the mass action law for semiconductors and explain the significance of each term. 5

c)    Design  the  doping  concentration  level  of  boron  ions  to   obtain  the conductivity of extrinsic silicon of 100 (am)- 1. Assume the mobility of holes is 0.05 m2 / Vs.  8

d)   Determine the position of the Fermi level (in eV) from the valence band edge for the semiconductor in c). Is this an n- or p-type semiconductor?  8

e)    Draw  an  energy  band  diagram  for  a  pn  junction  under  the  zero  bias condition. Label the band edges, the extrinsic and intrinsic Fermi levels.  5

f)    You are asked to design an abrupt or step pn junction, with depletion region width of 0.2 µm, entirely on the n-type side of the junction. Assume the built-in potential across the junction, Vbi  = 0.7 V.

i)         What is the doping concentration of the n-type semiconductor that would meet this requirement? 7

ii)        Explain  how  the  depletion  width  would  change  if  the  doping concentration  calculated  in  i)  doubles.  State  the  value   of  the depletion width (in µm). 3

iii)       Illustrate, with the aid of a diagram, the space distribution of charge across the junction for the two scenarios given in i) and ii). 2

Total

40

b)   Derive  an  expression  for  the  threshold  voltage  of  an  ideal  p-type  MOS capacitor  in  terms   of  the  thickness   of  the  dielectric  (tox),  the  relative permittivity of the gate (εox) and the substrate (εs) materials, and the substrate doping concentration (NA): 10

VT = tox + 2φF .

c)    The MOS capacitor discussed in b) is to be designed so the threshold voltage is VT = 1 V.

i)         What is the gate oxide thickness for the MOS capacitor that would provide the required threshold voltage? Assume a p-substrate doping concentration of 1x1016 cm-3 and an ideal MOS capacitor. 5

ii)        Comment  on  the  gate  oxide  thickness  if the  doping  concentration increases 10x. 2

d)    Sketch the high frequency (1 MHz) and low frequency (1 kHz) capacitance voltage characteristics of a MOS capacitor. Label the accumulation, depletion and inversion regions on the characteristics. Explain why the capacitance in inversion for this device differs when measured at high and low frequencies. 6

Total

30

3.   a)    Briefly describe the fabrication of a p-channel MOSFET in an n-well. 3

b)   Develop an expression for the current flowing in the channel of an 10

n-MOSFET in terms of the gate, drain and threshold voltages, in the linear region:

ID = µCo [(VG - VT )VD - ],

where the symbols have their usual meanings. Define the device constant in the expression above.

c)    State  the  difference between  the enhancement and the depletion types of MOSFETs. Sketch the symbols and transfer characteristics of these two types of devices for p- and n-channel transistors.    5

d)   You are asked to design a CMOS inverter with a threshold voltage of 1.2 V. The inverter threshold voltage refers to the point on the inverter transfer characteristic where the transition from logic  1 to logic 0 (and vice versa) occurs, and where you would expect that both n- and p-channel MOSFETs work in their saturation regions.

Assume a power rail VDD = 3 V, threshold voltages of n- and p-MOSFETs are VTn  = 0.7 V, VTp  = -0.8 V respectively, (W/L)n  = 2 for the n-MOSFET, electron mobility µn = 545 cm2 / Vs and hole mobility µp  = 130 cm2 / Vs.

i)         What is the aspect ratio (W/L)p  for p-MOSFET that would meet this requirement? 8

ii)        Comment on the solution in i). Is this an optimal design solution? 2

e)    State the two key parameters which govern the speed of CMOS inverters. 2

Total

30