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Practice Questions

Digital Systems (ELEC ENG 2100)

Last revised: January 27, 2021

These exercises are intended to reinforce the learning outcomes from ELEC ENG 2100 Digital Systems.

Many of the exercises are drawn directly from the course textbook, Digital Design and Computer Architecture, by Harris and Harris (2nd Edition, 2013). These are identified by their original numbering in the form “[Exercise 1.1]” or “[Question 1.1]”. Additional questions are identified simply by a number. Solutions to all of the textbook exercises are provided on MyUni. Answers for all of the other exercises (except the Brain Extenders and Digital Design Challenges) are also available in a separate file on MyUni.

All of these exercises (excluding the Brain Extenders and Digital Design Challenges) are representative of questions in the final exam.

At the end of this document are some Brain Extenders and Digital Design Challenges. These are useful, interesting and challenging exercises intended to further develop the learning objectives of the course. They are, however, less like questions you can expect in the final exam.

Topic 1: Building Digital Systems

Managing complexity: abstraction, discipline, hierarchy, regularity and modularity

Question 1. Design a digital system involves trading many di↵erent goals. What are 5 common goals in digital systems design? Explain each in a sentence or two.

Question 2. Why are digital systems becoming more complex?

Question 3. [Exercise 1.1] Explain in one paragraph at least three levels of abstraction that are used by:

a) biologists studying the operation of cells;

b) chemists studying the composition of matter.

Question 4. One approach to digital systems design involves progressively refining the abstraction of the system. Explain how you might design the circuit for digital watch using this approach. What are the main di↵erent levels of abstraction you would use?

Question 5. [Exercise 1.2] Explain in one paragraph how the techniques of hierarchy, modularity, and regularity may be used by:

a) automobile designers;

b) businesses to manage their operations.

Question 6. The Windows Explorer is shown below. Does it use abstraction or hierarchy or both? How? Why?

Question 7. One division of layers of abstraction in digital systems is: requirements, specification, architecture, micro-architecture, logic and digital circuit. At the digital circuit level the system might be described in terms of transistors. In what terms might the circuit be described at the other levels of abstraction?

Question 8. [Exercise 1.3] Ben Bitdiddle is building a house. Explain how he can use the principles of hierarchy, modularity, and regularity to save time and money during construction.

Question 9. What is discipline in engineering design? Why is it used? The lecture notes and textbook contain explains of discipline. Can you think of another?

Question 10. Discipline is about restricting design choices. What choices are restricted in the digital discipline?

Question 11. How would you partition the digital circuit for a digital thermometer? Use diagrams to clarify your answer.

Question 12. A 2 by 4-bit register circuit is shown below. It is made from 2 inverters (INV), 4 AND2 gates, 8 D flip-flops (FLOPS), and 8 tristate bu↵ers (TRI). Do not worry about how these blocks work.

a) The circuit on the left below shows how an AND4 cell can be built using AND2 cells which are, in turn, built from a NAND2 cell and an INV cell. The corresponding hierarchy can be described by the tree diagram to the right. Draw a tree diagram like this to show how you would partition the register file into a hierarchy.

b) List 4 benefits of using a hierarchy like this. Explain each in a few short sentences.

The digital abstraction: digital signals, logic gates

Question 13. What is the digital abstraction?

Question 14. A binary signal has value 0. What other words do we commonly use to describe its state?

Question 15. [Exercise 1.4] An analog voltage is in the range of 0-5 V. If it can be measured with an accuracy of ±50 mV, at most how many bits of information does it convey?

Question 16. [Exercise 1.5] A classroom has an old clock on the wall whose minute hand broke o↵.

a) If you can read the hour hand to the nearest 15 minutes, how many bits of information does the clock convey about the time?

b) If you know whether it is before or after noon, how many additional bits of information do you know about the time?

Question 17. Many electronic systems that were once analog are now digital.

a) What is the di↵erence between analog and digital electronics?

b) What are some of the benefits of digital systems that explain the trend away from analog systems?

c) Identify a situation in which it is still best (or perhaps necessary) to use analog electronics.

Question 18. [Exercise 1.71] Draw the symbol, Boolean equation, and truth table for:

a) a three-input OR gate;

b) a three-input exclusive OR (XOR) gate;

c) a four-input XNOR gate.

Question 19. [Exercise 1.73] A majority gate produces a TRUE output if and only if more than half of its inputs are TRUE. Complete a truth table for the three-input majority gate shown in Figure 1.41.

Question 20. [Exercise 1.74] A three-input AND-OR (AO) gate shown in Figure 1.42 produces a TRUE output if both A and B are TRUE, or if C is TRUE. Complete a truth table for the gate.

Question 21. [Exercise 1.75] A three-input OR-AND-INVERT (OAI) gate shown in Figure 1.43 produces a FALSE input if C is TRUE and A or B is TRUE. Otherwise it produces a TRUE output. Complete a truth table for the gate.

Question 22. [Exercise 1.76] There are 16 di↵erent truth tables for Boolean functions of two variables. List each truth table. Give each one a short descriptive name (such as OR, NAND, and so on).

Question 23. Write Boolean functions for W , X, Y , and Z in the circuit below.

Question 24. Draw a circuit diagram using AND, OR and NOT gates for the following Boolean functions. There is no need to simplify the functions.

a) Y = A.B + A.B

b) Y = A.(B + C)

c) Y = A.C + B.D

Question 25. Write a truth table for the Boolean functions in the previous question.

The digital abstraction: number systems

Question 26. [Exercise 1.6] The Babylonians developed the sexagesimal (base 60) number system about 4000 years ago. How many bits of information are conveyed with one sexagesimal digit? How do you write the number 400010 in sexagesimal?

Question 27. [Exercise 1.7] How many di↵erent numbers can be represented with 16 bits?

Question 28. [Exercise 1.8] What is the largest unsigned 32-bit binary number?

Question 29. [Exercise 1.9] What is the largest 16-bit binary number that can be represented with

a) unsigned numbers?

b) two’s complement numbers?

c) sign/magnitude numbers?

Question 30. [Exercise 1.11] What is the smallest (most negative) 16-bit binary number that can be represented with

a) unsigned numbers?

b) two’s complement numbers?

c) sign/magnitude numbers?

Question 31. [Exercise 1.13] Convert the following unsigned binary numbers to decimal.

a) 10102

b) 1101102

c) 111100002

d) 00011000101001112

Question 32. [Exercise 1.15] Repeat Exercise 1.13, but convert to hexadecimal.

Question 33. [Exercise 1.17] Convert the following hexadecimal numbers to decimal.

a) A516

b) 3B16

c) FFFF16

d) D000000016

Question 34. [Exercise 1.19] Repeat Exercise 1.17, but convert to unsigned binary.

Question 35. Convert the following numbers to decimal. Show working.

a) 1021123

b) 320145

c) 1210212 (This is an example of redundant number system. They are a bit obscure, but fun.)

Question 36. [Exercise 1.21] Convert the following two’s complement binary numbers to decimal.

a) 10102

b) 1101102

c) 011100002

d) 100111112

Question 37. [Exercise 1.23] Repeat Exercise 1.21, assuming the binary numbers are in sign/magnitude form rather than two’s complement representation.

Question 38. [Exercise 1.25] Convert the following decimal numbers to unsigned binary numbers.

a) 4210

b) 6310

c) 22910

d) 84510

Question 39. [Exercise 1.27] Repeat Exercise 1.25, but convert to hexadecimal. [And show working!]

Question 40. [Exercise 1.29] Convert the following decimal numbers to 8-bit two’s complement numbers or indicate that the decimal number would overflow the range.

a) 4210

b) −6310

c) 12410

d) −12810

e) 13310

Question 41. [Exercise 1.31] Repeat Exercise 1.29, but convert to 8-bit sign/magnitude numbers.

Question 42. [Exercise 1.33] Convert the following 4-bit two’s complement numbers to 8-bit two’s complement numbers.

a) 01012

b) 10102

Question 43. [Exercise 1.35] Repeat Exercise 1.33 if the numbers are unsigned rather than two’s complement.

Question 44. [Exercise 1.37] Base 8 is referred to as octal. Convert each of the numbers from Exercise 1.25 to octal.

Question 45. [Exercise 1.39] Convert each of the following octal numbers to binary, hexadecimal, and decimal.

a) 428

b) 638

c) 2558

d) 30478

Question 46. [Exercise 1.41] How many 5-bit two’s complement numbers are greater than 0? How many are less than 0? How would your answers di↵er for sign/magnitude numbers?

Question 47. [Exercise 1.43] How many bytes are in a 32-bit word? How many nibbles are in the word?

Question 48. [Exercise 1.44] How many bytes are in a 64-bit word?

Question 49. [Exercise 1.45] A particular DSL modem operates at 768 kbits/sec. How many bytes can it receive in 1 minute?

Question 50. [Exercise 1.47] Hard disk manufacturers use the term “megabyte” to mean 106 bytes and “gigabyte” to mean 109 bytes. How many real GBs of music can you store on a 50 GB hard disk?

Question 51. How many 16-bit words can be stored in a 4 kibibit memory?

Question 52. [Exercise 1.50] Draw a number line analogous to Figure 1.11 for 3-bit unsigned, two’s complement, and sign/magnitude numbers.

Question 53. [Exercise 1.52] Perform the following additions of unsigned binary numbers. Indicate whether or not the sum overflows a 4-bit result.

a) 10012 + 01002

b) 11012 + 10112

Question 54. [Exercise 1.53] Perform the following additions of unsigned binary numbers. Indicate whether or not the sum overflows an 8-bit result.

a) 100110012 + 010001002

b) 110100102 + 101101102

Question 55. [Exercise 1.54] Repeat Exercise 1.52, assuming that the binary numbers are in two’s complement form.

Question 56. [Exercise 1.56] Convert the following decimal numbers to 6-bit two’s complement binary numbers and add them. Indicate whether or not the sum overflows a 6-bit result.

a) 1610 + 910

b) 2710 + 3110

c) −410 + 1910

d) 310 − 3210

e) −1610 + −910

f) −2710 + −3110

Question 57. [Exercise 1.60] Convert the following decimal numbers to 5-bit two’s complement binary numbers and subtract them. Indicate whether or not the di↵erence overflows a 5-bit result.

a) 910 − 710

b) 1210 − 1510

c) −610 − 1110

d) 410 − −810

Question 58. Compare the relative costs and benefits of sign/magnitude and two’s complement binary numbers.

Question 59. Write a pseudo-code routine to convert numbers from binary to decimal. The binary number is input as X, an n-element array of bits. X[0] is the least significant bit. X[n-1] is the most significant bit.

Implementation technologies: discrete logic chips, microprocessors, gate arrays, pro-grammable logic controllers and custom VLSI

Question 60. You are building a digital radar signal processing system for an autonomous robot. You have already determined that the processing required would be best performed using an FPGA or an ASIC. What are the most important considerations in the decision between an FPGA or an ASIC?

Question 61. Your company “Starving Students pty ltd” has been approached by an inventor who believes there is a market for a small, hand-held electronic device for both tennis and cricket umpires. It would have 2 modes: a game/set counter mode for tennis; and an over counter for cricket. He expects to sell 5000 units in Australia.

What implementation technology would you use to build this device? Justify your answer in broad terms. Note that there is more than one correct answer!

Question 62. Suggest a digital system that would be appropriate to build using:

a) discrete logic chips

b) a microcontroller

c) an FPGA

d) a PLC

e) an ASIC

Question 63. For each of your answers to the previous question, summarise the reasons that make the imple mentation technology an appropriate choice.

Question 64. What is a microcontroller? How do microcontrollers di↵er from microprocessors?

Question 65. You work for a company that does contract designs of embedded digital systems. Your boss is sick of sending his sta↵ to training courses for di↵erent microcontrollers, not to mention purchasing programmers and debuggers for di↵erent microcontrollers. He has asked you to select a preferred microcontroller vendor for your company.

a) Discuss the challenges you face in completing this task.

b) List some of the considerations you will use to evaluate the di↵erent vendors.

Question 66. Microcontrollers often have integrated analog to digital converters. These could be used, for example, to read an analog sensor such as a temperature sensor. List two other peripherals one might find on a microcontroller and give examples of how they could be used.

Question 67. Just three of the many ways you can build a digital system are to use a microcontroller, an FPGA, or an FPGA configured to include a microprocessor. In very broad terms describe common circumstances in which you would choose each of these three options.

Introduction to SystemVerilog: signals, operators, continuous assignments, structural models, testbenches

Question 68. In previous questions we have considered the following layers of abstraction for digital systems: requirements, specification, architecture, micro-architecture, logic and digital circuit. At which of these levels of abstraction would it be useful to use SystemVerilog to capture the design?

Question 69. Hardware description languages (HDLs) are now widely used to describe digital systems. In many cases they have replaced the use of schematic diagrams. Suggest 3 reasons why using a HDL might be preferable to a schematic diagram. Are there any benefits to schematic diagrams?

Question 70. [Exercise 4.1] Sketch a schematic of the circuit described by the following HDL code. (If you can, simplify the schematic so that it shows a minimum number of gates.)

module exercise1 (input logic a, b, c,

output logic y, z);

assign y = a & b & c | a & b & ~c | a & ~b & c;

assign z = a & b | ~a & ~b;

endmodule

Question 71. [Exercise 4.3] Write an HDL module that computes a four-input XOR function. The input is a[3:0], and the output is y.

Question 72. Write a simple self-checking testbench for Exercise 4.3 that checks all 16 test cases.

Question 73. [Exercise 4.5] Write an HDL module called minority. It receives three inputs, a, b, and c. It produces one output, y, that is TRUE if at least two of the inputs are FALSE.

Question 74. [Exercise 4.6] Write an HDL module for a hexadecimal seven-segment display decoder. The decoder should handle the digits A, B, C, D, E, and F as well as 0–9.

Question 75. Write HDL modules that implement the following Boolean equations:

a) Y = A.C + B.C

b) Y = A

c) Y = A + B.C + B.D + B.D

Question 76. [Exercise 4.16] Write an HDL module that implements the circuit from Exercise 2.26. [Shown below.]

Question 77. [Question 4.1] Write a line of HDL code that gates a 32-bit bus called data with another signal called sel to produce a 32-bit result. If sel is TRUE, result = data. Otherwise, result should be all 0’s.

Question 78. [Question 4.3] What does the following SystemVerilog statement do?

result = | (data[15:0] & 16’hC820);

Question 79. If a = 1, b = 0, c = 1 and d = 1, what value is assigned to y in the following SystemVerilog modules?

a)

module exa(input logic a, b, c, d, output logic y);

assign y = a ? b : (c | d);

endmodule

b)

module exb(input logic a, b, c, d,

output logic [2:0] y);

assign y = a ? {b, c, d} : {d, c, b};

endmodule

c)

module exc(input logic a, b, c, d, output logic y);

assign y = a ? c : 1’bZ;

assign y = b ? 1’b0 : 1’bZ;

endmodule

d)

module exd(input logic a, b, c, d, output logic y);

assign y = a ? c : 1’bZ;

assign y = b ? 1’bZ : 1’b0;

endmodule

Question 80. Draw a circuit diagram corresponding to the following SystemVerilog.

module gate_a(input logic a, b, output logic y);

assign y = a ^ b;

endmodule

module gate_b(input logic a, b, output logic y);

assign y = a | b;

endmodule

module gate_c(input logic [3:0] a, output logic y);

assign y = ~&a;

endmodule

module cct(input logic c, d, e, f,

output logic z);

logic g, h;

gate_a g1(e, d, g);

gate_b g2(c, f, h);

gate_c g3({g, h, e, f}, z);

endmodule

Question 81. When using SystemVerilog for a digital design project it is important to write in an idiomatic way. In other words, while there may be many ways to express a particular function, it is important to choose one of the conventional or common ways. Why is this important?

Question 82. How is the hierarchy of a digital system represented in SystemVerilog?

Topic 2: Combinational Logic Design

Review: Boolean equations, Boolean algebra, simplification, Karnaugh maps Logic synthesis: manual techniques, combinational logic in SystemVerilog

Question 83. Do the following circuits satisfy the rules of combinational composition? Why (or why not)?

a)

b)

c)

Question 84. In the Boolean function Y = A.C + A.B.C identify:

a) a literal;

b) a literal in complementary form;

c) an implicant;

d) a minterm.

Question 85. [Exercise 2.1] Write a Boolean equation in sum-of-products canonical form for each of the truth tables in Figure 2.80.

Question 86. [Exercise 2.3] Write a Boolean equation in product-of-sums canonical form for the truth tables in Figure 2.80.

Question 87. [Exercise 2.5] Minimize each of the Boolean equations from Exercise 2.1.

Question 88. [Exercise 2.7] Sketch a reasonably simple combinational circuit implementing each of the functions from Exercise 2.5. Reasonably simple means that you are not wasteful of gates, but you don’t waste vast amounts of time checking every possible implementation of the circuit either.

Question 89. [Exercise 2.9] Repeat Exercise 2.7 using only NOT gates and AND and OR gates.

Question 90. [Exercise 2.11] Repeat Exercise 2.7 using only NOT gates and NAND and NOR gates.

Question 91. [Exercise 2.13] Simplify the following Boolean equations using Boolean theorems. Check for correctness using a truth table or K-map.

a) Y = A.C + A.B.C

b) Y = A.B + A.B.C + (A + C)

Question 92. [Exercise 2.15] Sketch a reasonably simple combinational circuit implementing each of the functions from Exercise 2.13.

Question 93. [Exercise 2.17] Simplify each of the following Boolean equations. Sketch a reasonably simple combinational circuit implementing the simplified equation.

a) Y = B.C + A.B.C + B.C

b) Y = A + A.B + A.B + A + B

c) Y = A.B.C + A.B.D + A.B.E + A.C.D + A.C.E + (A + D + E) + B.C.D + B.C.E + B.D.E + C.D.E

Question 94. [Exercise 2.33] Prove that the following theorems are true using perfect induction. You need not prove their duals.

a) The idempotency theorem (T3) [B.B = B]

b) The distributivity theorem (T8) [(B.C)+(B.D) = B.(C + D)]

c) The combining theorem (T10) [(B.C)+(B.C) = B]

Question 95. [Exercise 2.23] Prove De Morgan’s Theorem (T12) for three variables, B2, B1, B0, using perfect induction. [B0.B1.B2 = B0 + B1 + B2]

Question 96. [Exercise 2.24] Write Boolean equations for the circuit in Figure 2.82. You need not minimize the equations.

Question 97. [Exercise 2.25] Minimize the Boolean equations from Exercise 2.24 and sketch an improved circuit with the same function.

Question 98. [Exercise 2.26] Using De Morgan equivalent gates and bubble pushing methods, redraw the circuit in Figure 2.83 so that you can find the Boolean equation by inspection. Write the Boolean equation.

Question 99. [Exercise 2.27] Repeat Exercise 2.26 for the circuit in Figure 2.84.

Question 100. [Exercise 2.28] Find a minimal Boolean equation for the function in Figure 2.85. Remember to take advantage of the don’t care entries.

Question 101. [Exercise 2.29] Sketch a circuit for the function from Exercise 2.28.

Question 102. [Exercise 4.18] Write an HDL module that implements the logic function from Exercise 2.28. Pay careful attention to how you handle don’t cares.

Question 103. [Exercise 2.33] Ben Bitdiddle will enjoy his picnic on sunny days that have no ants. He will also enjoy his picnic any day he sees a hummingbird, as well as on days where there are ants and ladybugs. Write a Boolean equation for his enjoyment (E) in terms of sun (S), ants (A), hummingbirds (H), and ladybugs (L).

Question 104. [Exercise 2.34] Complete the design of the seven-segment decoder segments Sc through Sg (see Example 2.10): [The input is the 4-bit signal D3:0. The outputs are shown on Figure 2.47 below.]

a) Derive Boolean equations for the outputs Sc through Sg assuming that inputs greater than 9 must produce blank (0) outputs.

b) Derive Boolean equations for the outputs Sc through Sg assuming that inputs greater than 9 are don’t cares.

c) Sketch a reasonably simple gate-level implementation of part b). Multiple outputs can share gates where appropriate. [Use 2-level logic.]

Question 105. You have to implement a Boolean function of 5 variables using discrete logic chips. You suspect the function could be simplified. What are your options?

Question 106. A minimized equation in sum of products form uses the fewest possible implicants. Is this always the best form of the equation to implement? Explain your answer.

Question 107. A colleague has drawn the schematic below for your review. Provide them with some constructive feedback.

Question 108. Sketch a schematic for the Boolean equations X = D + E.F.G + B.F , and Y = B(C + D + E + F + G) using:

a) 2-level logic

b) inverters, 2-input OR gates and 2-input AND gates in as many levels as you require

Question 109. Show that the two circuits below implement the same Boolean function. Which is better? Why?

Question 110. [Exercise 2.35] A circuit has four inputs and two outputs. The inputs, A3:0, represent a number from 0 to 15. Output P should be TRUE if the number is prime (0 and 1 are not prime, but 2, 3, 5, and so on, are prime). Output D should be TRUE if the number is divisible by 3. Give simplified Boolean equations for each output and sketch a circuit. [Use 2-level logic.]

Question 111. [Exercise 4.19] Write an HDL module that implements the functions from Exercise 2.35.

Question 112. [Exercise 2.36] A priority encoder has 2N inputs. It produces an N-bit binary output indicating the most significant bit of the input that is TRUE, or 0 if none of the inputs are TRUE. It also produces an output NONE that is TRUE if none of the input bits are TRUE. Design an eight-input priority encoder with inputs A7:0 and outputs Y2:0 and NONE. For example, if the input is 00100000, the output Y should be 101 and NONE should be 0. Give a simplified Boolean equation for each output, and sketch a schematic.

Question 113. [Exercise 4.20] Write an HDL module that implements the priority encoder from Exercise 2.36.

Question 114. [Exercise 2.37] Design a modified priority encoder (see Exercise 2.25) that receives an 8-bit input, A7:0, and produces two 3-bit outputs, Y2:0 and Z2:0. Y indicates the most significant bit of the input that is TRUE. Z indicates the second most significant bit of the input that is TRUE. Y should be 0 if none of the inputs are TRUE. Z should be 0 if no more than one of the inputs is TRUE. Give a simplified Boolean equation for each output, and sketch a schematic.

Question 115. [Exercise 4.12] Write an HDL module for an eight-input priority circuit.

Question 116. [Exercise 2.38] An M-bit thermometer code for the number k consists of k 1’s in the least significant bit positions and (M − k) 0’s in all the more significant bit positions. A binary-to-thermometer code converter has N inputs and 2N − 1 outputs. It produces a 2 N − 1 bit thermometer code for the number specified by the input. For example, if the input is 110, the output should be 0111111. Design a 3:7 binary-to-thermometer code converter. Give a simplified Boolean equation for each output, and sketch a schematic.

Question 117. [Exercise 4.22] Write an HDL module that implements the binary-to- thermometer code converter from Exercise 2.27.

Question 118. [Question 2.1] Sketch a schematic for the two-input XOR function using only NAND gates. How few can you use?

Question 119. [Question 2.2] Design a circuit that will tell whether a given month has 31 days in it. The month is specified by a 4-bit input, A3:0. For example, if the inputs are 0001, the month is January, and if the inputs are 1100, the month is December. The circuit output, Y , should be HIGH only when the month specified by the inputs has 31 days in it. Write the simplified equation, and draw the circuit diagram using a minimum number of gates. (Hint: Remember to take advantage of don’t cares.)

Question 120. [Exercise 4.23] Write an HDL module implementing the days-in-month function from Question 2.2.

Question 121. [Question 2.4] A gate or set of gates is universal if it can be used to construct any Boolean function. For example, the set {AND, OR, NOT} is universal.

a) Is an AND gate by itself universal? Why or why not?

b) Is the set {OR, NOT} universal? Why or why not?

c) Is a NAND gate by itself universal? Why or why not?

Question 122. You have written a HDL module for some combinational logic. Your design amounts to tens of logic gates and will be implemented on an FPGA. A colleague, in a review of your design, points out that you could have minimised the Boolean logic you used in the HDL. Is this a serious shortcoming of your design? Explain your answer.

Question 123. The SystemVerilog module below contains one simple error.

module bcd_decoder(input logic a, b, c, d, output logic [9:0] y);

always @ (a, b, c)

begin

case ({a,b,c,d})

4’b0000: y = 10’b0000000001;

4’b0001: y = 10’b0000000010;

4’b0010: y = 10’b0000000100;

4’b0011: y = 10’b0000001000;

4’b0100: y = 10’b0000010000;

4’b0101: y = 10’b0000100000;

4’b0110: y = 10’b0001000000;

4’b0111: y = 10’b0010000000;

4’b1000: y = 10’b0100000000;

4’b1001: y = 10’b1000000000;

default: y = 10’b0000000000;

endcase

end

endmodule

The following test bench, although not a thorough test of the module, does expose the error.

module bcd_decoder_tb();

logic a, b, c, d;

logic [9:0] y;

bcd_decoder dut(a, b, c, d, y);

initial

begin

$display ("Beginning");

{a,b,c,d} = 4’b0000; #10;

if (y !== 10’b0000000001) $display ("test 1 failed");

{a,b,c,d} = 4’b0001; #10;

if (y !== 10’b0000000010) $display ("test 2 failed");

{a,b,c,d} = 4’b0011; #10;

if (y !== 10’b0000001000) $display ("test 3 failed");

{a,b,c,d} = 4’b0001; #10;

if (y !== 10’b0000000010) $display ("test 4 failed");

{a,b,c,d} = 4’b1111; #10;

if (y !== 10’b0000000000) $display ("test 5 failed");

{a,b,c,d} = 4’b1001; #10;

if (y !== 10’b1000000000) $display ("test 6 failed");

$display ("Ending");

end

endmodule

The simulator produces the following results:

Beginning

test 2 failed

Ending

a) What is the error in the SystemVerilog module?

b) What could you do to avoid errors like this?

c) If the uncorrected SystemVerilog module is passed to Synopsys design compiler, then a combinational logic circuit is produced. Does that surprise you? What is the problem here?

High impedance & illegal logic states

Combinational blocks: multiplexers, decoders, tristates

Question 124. When simulating a logic circuit you discover a signal that occasionally has the value X. Why is this a problem? What do you suspect is the cause of the problem?

Question 125. A 4 input multiplexer is shown below. Explain what it does in words. Write a truth table for the multiplexer.

Question 126. [Exercise 2.39] Write a minimized Boolean equation for the function performed by the circuit in Figure 2.87.

Question 127. [Exercise 2.40] Write a minimized Boolean equation for the function performed by the circuit in Figure 2.88.

Question 128. [Exercise 2.41] Implement the function from Figure 2.80 (b) [repeated below] using

a) an 8:1 multiplexer

b) a 4:1 multiplexer and one inverter

Question 129. [Exercise 2.42] Implement the function from Exercise 2.17(a) [Y = B + A.C] using

a) an 8:1 multiplexer

b) a 4:1 multiplexer and no other gates

Question 130. [Question 2.3] What is a tristate bu↵er? How and why is it used?

Question 131. A logic simulator produces the following output for a simulation of a tristate inverter. Is the output correct for time 2 ns to time 4 ns? Shouldn’t it be Z? What would you see if you built the circuit and measured Y with a CRO?

Question 132. The figure below shows two circuit boards. Due to a design oversight the boards are connected by a single wire. Sometimes board 1 must send a Boolean value to board 2. At other times board 2 must send a Boolean value to board 1. Specifically:

i) When D = 0, board 1 must put the logic signal A on the wire such that board 2 can read the value of A into input X.

ii) When D = 1, board 2 must put the logic signal B on the wire such that board 1 can read the value of B into input Y .

Assume the boards always agree on the value of D. Build a circuit to satisfy these requirements.

Question 133. The logic blocks A, B and C below need to exchange signals. blockA reads the signal inA when rdA is true. blockB and blockC operate similarly. When the Control block sets AtoBC, blockB and blockC should both read outA. When the Control block sets BtoAC, blockA and blockC should both read outB. When the Control block sets C toAB, blockA and blockB should both read outC.

a) Design a circuit to fulfil these requirements using tristate bu↵ers and any other logic you need.

b) Design another circuit to do the same thing using multiplexers instead of tristate bu↵ers.

c) Which of these two approaches is preferred contemporary design practice?

Question 134. Deign a schematic circuit for a 4-input multiplexer using tristate bu↵ers.

Question 135. Design a schematic circuit for an 8-input multiplexer using 2-input multiplexers.

Question 136. Use the following template to draw a circuit for a 3:8 decoder using 2-level logic. (You just need to draw dots to join wires.)

Question 137. [Exercise 4.2] Sketch a schematic of the circuit described by the following HDL code. Simplify the schematic so that it shows a minimum number of gates.

module exercise2 (input logic [3:0] a,

output logic [1:0] y);

always_comb

if (a[0]) y = 2’b11;

else if (a[1]) y = 2’b10;

else if (a[2]) y = 2’b01;

else if (a[3]) y = 2’b00;

else y = a[1:0];

endmodule

Question 138. [Exercise 4.8] Write an 8:1 multiplexer module called mux8 with inputs s2:0, d0, d1, d2, d3, d4, d5, d6, d7, and output y.

Question 139. [Exercise 4.9] Write a structural module to compute the logic function, Y = A.B +B.C +A.B.C, using multiplexer logic. Use the 8:1 multiplexer from Exercise 4.8.

Question 140. [Exercise 4.10] Repeat Exercise 4.9 using a 4:1 multiplexer and as many NOT gates as you need.

Question 141. [Exercise 4.13] Write an HDL module for a 2:4 decoder.

Question 142. [Exercise 4.14] Write an HDL module for a 6:64 decoder using three instances of the 2:4 decoders from Exercise 4.13 and a bunch of three-input AND gates.

Question 143. Microcontrollers often have digital I/O pins that can be configured to be either inputs or outputs. A typical arrangement is shown as a schematic below. The 8-bit port A[7:0] has a data direction control input D[7:0]. When D[i] is low, A[i] is an input and the value of A[i] appears at Ain[i]. When D[i] is high, A[i] is an output and is set to the value of Aout[i] (and the value of A[i] still appears at Ain[i]). Write a behavioural SystemVerilog module for this block. (Bonus: test benches for bidirectional or tristate signals are tricky. Can you write one to thoroughly test your block?)

Question 144. You are designing a toy racing car set. One of the controllers has 3 states—stop, go and caution—indicated by a 2-bit state vector S as shown below.

a) Draw a circuit to produce the red, green and amber signal for a traffic light. Use any standard digital logic blocks (e.g. multiplexers, gates etc...) that will do the job.

b) Write a SystemVerilog model for your circuit.

Question 145. It is the year 2084 and society as we know it has broken down. Mad Max has asked you to fix the logic circuit in his auto-loading crossbow. All you can find are a pile of 3 input OR gates and a 4-input decoder. Design a circuit to realise Y = A(B + C.D) + CB.

Timing: propagation delay, contamination delay, glitches

Question 146. A timing diagram for logic circuit with a 3-bit input (A2:0) and output (Y ) is shown below.

a) Draw arrows on the diagram to show the contamination delay and propagation delay for the circuit.

b) Estimate the contamination delay and propagation delay for the circuit in ps.

Question 147. The circuits below implement the same Boolean function. Do they have any potential glitches when one of the inputs changes? If not, explain why not. If so, show how to modify the circuit to eliminate the glitches.

Question 148. [Exercise 2.44] Determine the propagation delay and contamination delay of the circuit in Figure 2.83 [repeated below]. Use the gate delays given in Table 2.8.

Question 149. You build the circuit from Exercise 2.44 (above) and measure the contamination and propagation delays using a CRO. You find these di↵er from the numbers you calculated by around 20%.

a) Explain this variation if the circuit was operating under the same range of environmental conditions as specified for Table 2.8.

b) What if the circuit was operating under a di↵erent set of environmental conditions? What environmental factors could contribute the variation observed?

Question 150. [Exercise 2.45] Sketch a schematic for a fast 3:8 decoder. Suppose gate delays are given in Table 2.8 (and only the gates in that table are available). Design your decoder to have the shortest possible critical path, and indicate what that path is. What are its propagation delay and contamination delay?

Question 151. [Exercise 2.48] Design an 8:1 multiplexer with the shortest possible delay from the data inputs to the output. You may use any of the gates from Table 2.7. Sketch a schematic. Using the gate delays from the table, determine this delay.

Question 152. Your 8:1 multiplexer from Exercise 2.48 was optimised for minimum delay from data inputs to output. It is the best 8:1 multiplexer for this technology? Explain your answer.

Question 153. [Question 2.5] Explain why a circuit’s contamination delay might be less than (instead of equal to) its propagation delay.

Question 154. [Exercise 3.16] Suppose a ring oscillator is built from N inverters connected in a loop. Each inverter has a minimum delay of tcd and a maximum delay of tpd . If N is odd, determine the range of frequencies at which the oscillator might operate.

Question 155. [Exercise 3.17] Why must N be odd in Exercise 3.13?

Question 156. The figures below show a logic circuit and the results of a simulation.

a) Is the circuit producing the correct outputs for the inputs shown?

b) What is happening to the output y between time 2 ns and time 2.5 ns?

c) Explain the behaviour observed between time 1 ns and time 1.5 ns.

d) Comment on the signal y before time 0.5 ns. Suggest what is going on here?