CE339 “Billiards” video game
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CE339
Reassessment: “Billiards” video game
Assignment objectives
This document speciies the coursework assignment to be submitted by students taking CE339. This assignment is meant to provide an opportunity to improve the knowledge of the VHDL language and, more importantly, to design a digital “system”. You will be expected to learn to: a) implement digital system design in VHDL code; b) synthesise and download it to the target hardware; c) test, debug, and verify that the design meets the speciications; d) report about your design.
You are required to design code for your target hardware (a Digilent Basys3 board with a xilinx Artix 7 FPGA) in order to implement a design that meets the speciications (below). You are required to submit working and correct code and you are strongly encouraged to use a modular coding style (allowing for greater lexibility, maintainability, modularity, and reusability). To show that you master all aspects of the language, your code should prevalently use concurrent statements for combinatorial circuits and sequential code for sequential circuits. Additionally, the use of non- standard packages (e.g. STD-LOGⅠC-ARⅠTH, STD-LOGⅠC-UNSⅠGNED, STD-LOGⅠC-SⅠGNED) and BUFFER ports is forbidden, while the use of ⅠNOUT ports is accepted only when strictly necessary.
You are supposed to gain familiarity with VHDL coding during the supporting CE339 lectures and through self-study hours, also with the help of the recommended textbooks or any other book about VHDL. You are expected to work on this assignment mostly in labs. Your design project should be stored under the revision-control repository you were assigned at the beginning of the course. You are supposed to commit often and describe your progress in the commit messages. In order to promote a learning scheme that values the learning process in addition to the submitted inal design, your weekly progress (as traced back by the commit logs) will contribute to your assignment mark.
Design speciications
Your task for this assignment is to implement a “billiards” video game, and speciically a simpliied one-player version of “ive-pin billiards” (https://en.wikipedia.org/wiki/Five–pin-billiards). In this simpliied variant of the game, the layout includes a bordered pocketless table, a cue ball and ive pins. The shapes representing these elements can be very simple, like those in the mock-up in Figure 1.
During the game, the player determines the ball,s initial direction and velocity using the board,s buttons and/or switches (it,s your job to ind an intuitive way to do so without making the game trivial). The ball bounces of the cushions delimiting the playing surface until it loses speed and
stops. At the centre of the table there are ive pins positioned as in Figure 1. The player scores points by causing the ball to knock over pins, according to the following rules: a) each white pin is worth two points; b) the red pin is worth ten points if it is the only pin knocked down (by the ball going between the set of pins and narrowly missing all of the whites) and four points otherwise. points are earned when the ball hits the pins after bouncing at least once and they are lost when the ball hits the pins directly1. The points can be shown on the board,s 7-segment display.
To make the assignment feasible within the timeframe available for this module, you are allowed to implement a simpliication of the game. For example, it is advised to start with the cue ball moving in a straight hard-coded direction within an ininite playing surface, then implement elastic frictionless bounces on the cushions. Subsequently, you should let the player choose the initial direction and velocity of the ball as if the ball was hit by the cue stick. Finally, you can add the pins and detect contact between the ball and the pins to score points.
These speciications should be intended as guidelines and should not constrain you from improv- ing the game by designing better graphics, implementing more realistic physics, adding an object ball and a second player, and introducing other modiications that you think would result in a better “product” .
Report
you should write a report introducing the project and then describing your codings and designs for the assignment. It should irst describe the design at a higher level and then detail the implemen- tation of each module in a top-down fashion (rather than in chronological order). Also report if your code worked at the irst attempt, what was wrong and how you ixed it. The repository log (if you used it properly) should help you considerably in this task. your report should also include a discussion of design alternatives that you considered and the motivations for your inal choice.
your document should have a title page and be sub-divided into appropriately headed sections. It MUST contain references to material used in your work (e.g., VHDL code or information available in books or on the Internet). All of the VHDL code submitted should be included in the report in the form of code appendices and be typeset in courier font (or a suitable ixed-width alternative font of your choice). your report should consist of approximately 15oo-3ooo words of narrative (i.e. excluding references, code fragments, pictures, diagrams and schematics). please write registration number and word count on the title page of your report.
submission
Your work must be submitted to the university,s online FASer submission system at the address https://faser.essex.ac.uk/ by the deadline given on the system. No other mode of submission is acceptable. You are strongly advised to upload a draft submission before the last lab hours prior to the deadline, and then update it up to the deadline.
You are required to submit one ZIP archive (not RAR or other formats) containing the following iles:
1. All source iles needed to synthesize your project (but not the temporary iles created by Xilinx);
2. A report document submitted in PDF format. DO NOT SUBMIT THIS FILE IN .DOC OR .DOCX OR SIMILAR FORMATS - SUBMIT PDF.
3. Your repository log in .TXT/image format.
4. If you want (in your own interest, see next section), submit a .TXT or .PDF ile with the transcripts of relevant forum discussions you contributed to.
DO NOT WAIT UNTIL CLOSE TO THE DEADLINE TO MAKE YOUR FIRST SUBMIS- SION. Di伍culties with the submission system will not be accepted as an excuse for a missing submission.
Marking criteria
This assignment is worth 100% of the module mark. Marks will be awarded for the VHDL code, including coding style and quality, and for the descriptive document, including content, presentation, and discussions. In particular, marks will be assessed based on:
. Implementation
- Quality of the implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20%
- Modular design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10%
- Generic and re-usable code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%
- Proper use of comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8%
- Steady progress, adequate use of Gitlab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6%
. Report
- Correctness and completeness of report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12%
- Clarity of presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12%
- Organisation of report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12%
- Quality of diagrams and schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8%
. Others
- Compliance with submission instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2%
2023-07-31