Please submit your answer with a single PDF via the course site. You should use VCS to answer Question 3 and 4.

1.    Sketch a transistor-level schematic for a compound CMOS logic gate for each of following          functions (size the transistor widths to achieve effective rise and fall resistances equal to a unit inverter (R). You may have different circuit implantations, please use the least number of          transistors.

Unit nMOS has resistance R, capacitance C

Unit pMOS has resistance 2R, capacitance C

F = a + b . c,

F = abc + d

F = abc + abd + acd + bcd

2.    Please size the transistor width to achieve effective rise and fall resistances equal to a unit         inverter (R) for the 4-input NOR gate, mark the capacitance for each terminal, and calculate the delays for the following cases assume h identical such NOR gates are driven by the 4-input NOR gate: (a) best-case output falling delay; (b) best-case output rising delay; (c) worst-case output  falling delay; (d) worst-case output rising delay. Note you should specify how the input pattern changes for each case and explain the corresponding reason.

3.    (VCS Simulation) Write an RTL code and gate level Verilog code to implement the 4 to 1 Mux. Note that for gate level, you only have basic gates from the design library, such as AND, OR,   NOT, XOR etc. (The basic gates could have multiple bits input, for example two input or three input AND gate: a&b or a&b&c). The input and output signals are defined as follows:

Input: D0, D1, D2, D3, S0, S1 (S0, S1 select signals)

Output: Z

For the two implementations: (a) Draw the structure schematic; (b) Write your Verilog code and the testbench; (c)  Simulate and Validate them with VCS; (d) Compare the differences between  those two implementations (RTL vs Gatelevel);

All design structures, source codes and simulated waveforms should be included in your answer.