1. Objectives

The objective of this assignment is to complete, simulate in Modelsim/QuestaSim and validate two SystemC designs in order to achieve the required functionality. The assignment will be assessed based on your report. In the report you need to include evidence that your  designs compile successfully and achieve the intended functionality.

The assignment is worth 20% of the module marks and should take about 20 hours to complete.

You may discuss the assignment with other students, but the final code that you will be submitting for assessment must be your own work. Please ensure you are familiar with the rules on academic integrity and the penalties for violating those rules.

2. Assignment Requirements

The provided designs and the required extended functionality are:

Design 1: A full-adder design with the test bench is given (files: Adder.h, AdderMain.cpp, TestbenchDesign1.h has been provided):

Requirement 1.a: Modify the test bench in order to validate the correct operation of the design.

Requirement 1.b : Report  any erroneous behaviour you might observe in the simulation of the adder. If your find errors, identify the reasons and, if possible, correct them.

Design 2: A SystemC model of an 8-bit counter is provided (files Counter8bit.h,

CounterMain.cpp and TestbenchCounter.h). This design is incomplete and must be completed in order to operate as an 8-bit counter. The files contain an extensive set of internal comments with instructions for you to follow.

Requirement 2.a: Follow the instructions in the comments in order to complete the design in SystemC.

Requirement 2.b : Simulate your code and validate the correct operation of your design