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Principles of Computer Architecture – Spring 2023

Homework 4

1. A signal from the control block namely bne is taken and the zero output from the ALU is passed through a not gate is taken as an input to an and gate and the result is passed as an input to an or gate. The other input will be the already exisHng add gate with  input as the branch signal and the zero from the ALU . This is passed on as the control signal of the Mux.  In summary the branch mux select line has the following logic:  mux_sel = (Branch & Zero) | (BranchNotEqual & !Zero).

2.

3. No new blocks are needed to add to support execuHon of the instrucHon.

4. No new control signals are needed from the control unit to support the instrucHon.

5.

6.  Processor P2 has the highest performance expressed in IPS.

P1: 2 * 109

P2: 2.5 * 109

P3:  1.82 * 109

7.  Number of cycles : 30*109

     Number of Instruc8ons : 20 *109

8. Clock rate : 5.14GHz