Introduction

In this assessment, you are to work individually. You will be required to complete a number of tasks, written in SystemVerilog using ModelSim (Starter Edition).

Equipment and Software needed:

The only equipment needed is as follows:

PC running Windows 10 or 11

Quartus 20.1

ModelSim (Starter Edition)

GitHub Desktop

Starter Code

You must use the code provided on GitHub Classroom. Click the following link:

GitHub Classroom

This will create a private repository with the starter code.

Tasks

You should complete as many tasks as you can. Some marks may be awarded for partial solutions.

Each task is described in this document. The starter files are provided for each task are in the starter code. You should always use the files provided. In addition, you should read any comments in each  file.

The tasks are summarised as follows:

Task 1 – Combinational Logic Module with Test-bench – 20%

Task 2 – Sequential Logic Task and Test-bench – 25%

Task 3 – System Design Task with Test-bench – 25%

Task 4 – Controller Data Path Design (advanced) – 15%

Task 5 - Personal Management and Version Control – 15%

Details are given later in this document.

Assessment

Tasks 1-4 will be assessed through simulation and inspection of sources. For full marks, each Unit     Under Test (UUT) must be fully functional. Test-benches much provide the coverage specified in the task. All HDL must be commented and structured (including indentation). Personal Management and Version control will include evidence that you have followed good practise (see page 15). Your         version control history will be scrutinised.

Table 1: Assessment Weightings

IMPORTANT - What to Submit

Tasks 1-4: Complete the form tasks.docx which includes your GitHub URL and a declaration of which tasks you have attempted. Without the URL, the tutor cannot mark your work.

Task 5: Complete the document management.docx. Do not exceed one side of A4 and do not change the formatting styles.

Do NOT modify the code in your GitHub repository beyond the deadline. Any commits beyond the deadline will be disregarded.

You must“tag”your final submission that you wish to be assessed. See point 5 in the section “Personal Workflow” on page 15.

As a backup, it is strongly recommended you zip your SystemVerilog files and submit alongside the above. Where you have used Quartus, please delete any subfolders that are not required (those   created by Quartus).

Task 1 – Combinational Logic Module with Test-Bench –

20%

Consider the truth table for some combinational logic below, where A, B and C are 1-bit inputs and Y is a 1-bit output.

Table 2: Truth Table. A, B and C are 1-bit inputs. P and Q are 1-bit outputs.

The state ‘-’ denotes a don’t care.

Your tasks are as follows:

i.    Perform logic simplification for both logic circuits (one for output P; one for output Q)

ii.   Write two component modules, both which implement the combinational logic in table 2.

The first task1a.sv must use structural HDL.

The second task1b.sv may use a different style (dataflow or behavioural)

iii.  Write a test-bench task1_tb.svto do the following:

Exhaustively test task1a to confirm the outputs are correct for all input combinations.

Automatically check the outputs P and Q using the assert command. Write errors to the console if the wrong output is discovered.

Show that for all possible inputs, task1a has an identical output to task1b. Write errors to the console if the wrong output is discovered (using the assert command).

Make sure your modules and test-bench are sufficiently commented and correctly laid out.

Task 2 – Sequential Logic Task and Test-bench – 25%

This task is to create and test a 16-bit binary counter that counts from 0 to N-1, then recycles back to zero (where N is a parameter). The module outline is show in figure 1. The inputs and outputs are     described in table 3.

Table 3: input and Output signals for Task 2

Viewed as a schematic, the module can be represented as shown in figure 1.

Figure 1. 16-bit counter that re-cycles

when the count = N-1.

Key Points

You are to complete both the module (task2.sv) and it’s test-bench (task2_tb.sv). Try to evidence the full functionality of this module (as much as you can).

You must comment your test-bench, explaining WHAT is it you are testing

You should automate your tests using assert and include appropriate error messages.

The reset is asynchronous. It takes priority of all other inputs.

The prefix n_ is used to indicate active LOW.

An example timing diagram is shown below in figure 2.

Figure 2: Example timing diagram (N=16)

Task 3 – Moore Machine with Test-bench (25%)

In this task, you will use both sequential logic and combination logic to create and test a Finite State Machine. The state transition table is given below in table 4.

Table 4: State Transition Table. The system has a single 1-bit input X and a single 1-bit output Y.

You tasks are as follows:

i.    Without minimisation, complete moore_v1.sv and build the state machine for table 4 using SystemVerilog. Do not simplify at this stage.

ii.   Complete the test-bench moore_tb.sv to verify the behaviour of (i)

iii.  Use state-minimisation to reduce the number of Moore states in table 4 as much as possible. From this, build a reduced machine as module moore_v2.sv using SystemVerilog.

iv.  Modify the test bench in (ii) to compare the outputs of both moore_v1 and moore_v2 and show they are equivalent.

Task 4 – Controller Data Path Design (advanced) – 15%

You are to complete a design that constructs 8-bit bytes from 2 sequential 4-bit words. The design is partially completed (see figure 3). The timing diagram and annotation for the overall system is shown in figure 4. Some of this is already completed (do NOT modify anything unless specifically instructed to do so).

A summary of your tasks are:

◦  Complete the controller module in sequencer.sv

◦  Create a test-bench sequencer_tb.sv to evidence correct operation.

◦  Create a test-bench  system_tb.sv to evidence the complete system (shown in figure 2) is working1 .

Start by open the Quartus project file in the folder Task-4. Now read the following for a detailed specification of how this should operate.