1. Objectives

The purpose of this project is to design, simulate, implement, and verify a Simple RISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.  You are to use the Intel Quartus II design software for this purpose. The system is to be implemented on the Cyclone III chip (EP3C16F484) of theDE0 evaluation board or on the Cyclone V chip (5CEBA4F23C7) of theDE0-CV evaluation board.

The Mini SRC is similar to the SRC described in the Lab Reader, reproduced from the text by Heuring and Jordan.  The Datapath, Control Unit, and Memory Interface for Mini SRC have the same relationship as shown in Figure 4.1 on page 142 of the Lab Reader for the SRC system. The processor design is similar to the information presented in Figures and Tables on pages 143 through 167 of the Lab Reader .  As part of the learning process for the CPU design project, make sure you carefully read the Mini SRC CPU Specification (this document) and the descriptions of  different  lab  phases,  consult the Lab Reader, refer to the tutorial on Intel Quartus II, ModelSim-Altera and DE0/DE0-CV evaluation boards,the tutorial on CPU Design Project, and read the Lecture Slides on Computer Arithmetic, VHDL, and Verilog.

2. Processor Specification

The Mini SRC is a 32-bit machine, having a 32-bit datapath and sixteen 32-bit registers R0 to R15, with R0 to R7 as general-purpose registers, R8 to R11 as the argument registers, R12 and R13 as the return value registers, R14 as the stack pointer (SP), and R15 as the return address register (RA), holding the return address for a jal instruction. It also has two dedicated 32-bit registers HI and LO for multiplication and division instructions . Note that Mini SRC does not have a condition code register.  Rather, it allows any of the general-purpose registers to

hold a value to be tested for conditional branching.  The memory unit is 512 words.

The following is a formal definition of the Mini SRC.

Processor State

PC<31..0>:

IR<31..0>:

R[0..15]<31..0>:

R[0..7]<31..0>:

R[8..11]<31..0>:

R[12..13]<31..0>:

R[14]<31..0>:

R[15]<31..0]:

HI<31..0>:

LO<31..0>:

32-bit Program Counter (PC)

32-bit Instruction Register (IR)

16  32-bit registers, named R[0] through R[15]

Eight general-purpose registers

Four Argument Registers

Two Return Value Registers

Stack Pointer (SP)

Return Address Register (RA)

32-bit HI Register dedicated to keep the high-order word of a Multiplication product, or the Remainder of a Division operation

32-bit LO Register dedicated to keep the low-order word of a Multiplication product, or the Quotient of a Division operation

The Arithmetic Logic Unit (ALU) performs 13 operations: addition, subtraction, multiplication, division, shift right, shift right arithmetic, shift left, rotate right, rotate left, logical AND, logical OR, Negate (2’s complement), and NOT (1’s complement).

The instructions in Mini SRC are one-word (32-bit) long each.  They can be categorized as Load and Store instructions,  Arithmetic  and  Logical  instructions,  Conditional  Branch  and  Jump  instructions,  Input/Output instructions, and miscellaneous instructions. There are no push and pop instructions (they can be implemented by other instructions).  The following six addressing modes are supported: Direct, Indexed, Register, Register Indirect, Immediate, and Relative.

2.1 Instruction Formats

There are five instruction formats, as shown in the table below.

The instruction formats for different categories are detailed below:

•   Load and Store instructions: operands in memory can be accessed only through load/store instructions.

(a)  ld, ldi, st                               I-Format

31                 27 26       23 22        19 18                                                                                              0

•   Arithmetic and Logical instructions:

(a)  add, sub, and, or, shr, shra, shl, ror, rol                 R-Format

31                 27  26      23  22        19 18         15 14                                                                           0

(b) addi, andi, ori

31

I-Format

23  22       19  18

0

(c)  mul, div, neg, not

27  26

I-Format

23  22       19 18

0

•   Branch instructions: brzr, brnz, brmi, brpl                         B-Format

31

27  26      23  22       19  18

0

•   Jump instructions: jr, jal                J-Format

31

27  26        23  22

0

•   Input/Output and MFHI/MFLO instructions: in, out, mfhi, mflo              J-Format

31

27  26        23  22

0

•   Miscellaneous instructions: nop, halt

27  26

M-Format

0

Op-code:  Ra, Rb, Rc: C:

C2:

Notation:

specifies the operation to be performed.

0000: R0, 0001: R1, …, 1111: R15

constant (data or address)

2.2 Instructions

The instructions (with their op-code patterns shown in parentheses) perform the following operations:

Load and Store Instructions

ld, ldi, st:

ld: Load Direct

(00000xxxx0000xxxxxxxxxxxxxxxxxxx)

R[Ra] M[C (sign-extended) ]     Direct addressing, Rb = R0

Assembly language

ld          Ra, C

ld: Load Indexed/Register Indirect

(00000xxxxxxxxxxxxxxxxxxxxxxxxxxx)

R[Ra] M[R[Rb] + C (sign-extended)]           ld

Indexed addressing, Rb ≠ R0

If C = 0 ➔ Register Indirect addressing

Ra, C(Rb)

ldi: Load Immediate

(00001xxxx0000xxxxxxxxxxxxxxxxxxx)

(00001xxxxxxxxxxxxxxxxxxxxxxxxxxx)

R[Ra] C (sign-extended)                     Immediate addressing, Rb = R0

R[Ra] R[Rb] + C (sign-extended)       Immediate addressing, Rb ≠ R0

ldi

ldi

Ra, C

Ra, C(Rb)

If C = 0 ➔ instruction acts like a simple register transfer  If C ≠ 0 and Ra = Rb ➔ Increment/decrement instruction

st: Store Direct

(00010xxxx0000xxxxxxxxxxxxxxxxxxx)

st: Store Indexed/Register Indirect

(00010xxxxxxxxxxxxxxxxxxxxxxxxxxx)

Indexed addressing, Rb ≠ R0

If C = 0 ➔ Register Indirect addressing

C, Ra

C(Rb), Ra

Arithmetic and Logical Instructi