EEE339 DIGITAL SYSTEM DESIGN WITH HDL
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1st SEMESTER 2021/22 FINAL EXAMINATION
BACHELOR DEGREE – Year 4
EEE339
DIGITAL SYSTEM DESIGN WITH HDL
1 This question is not publishable.
2 According to the simulation waveforms for the inputs and outputs of a circuit, as shown in Figure Q2, decide the function of the circuit and write Verilog code for the circuit. clk and clr are inputs. q and C are outputs.
Figure Q2
3 (a) Consider the following Verilog code. What type of the circuit does the code represent? What is the output Y if more than one bit in the input W is 1?
(b) Modify the Verilog code using a casex statement so that a more significant bit poistion will be favoured when more than one bit in W is 1. Set an output z to 1 whenever at least one bit in W is 1.
(c) Rewrite the Verilog code derived from (b) using a for loop.
module test (W, Y);
input [7:0] W;
output reg [2:0] Y;
always @(W)
case (W)
8’b00000001: Y = 3’b000;
8’b00000010: Y = 3’b001;
8’b00000100: Y = 3’b010;
8’b00001000: Y = 3’b011;
8’b00010000: Y = 3’b100;
8’b00100000: Y = 3’b101;
8’b01000000: Y = 3’b110;
8’b10000000: Y = 3’b111;
default: Y = 3’bxxx;
endcase
endmodule
4 A finite state machine (FSM) is defined by the following state assignment table. Write Verilog code for this FSM.
Present state y2y1 |
Next state |
Output z |
|
w = 0 |
w = 1 |
||
Y2Y1 |
Y2Y1 |
||
00 |
10 |
11 |
0 |
01 |
01 |
00 |
0 |
10 |
11 |
00 |
0 |
11 |
10 |
01 |
1 |
5 (a) The CPI of three instruction types A, B and C on machine M1 are as follows: CPIA = 1.2, CPIB = 2.3, CPIC = 1.7. What is the average CPI of machine M1
for a programme with 22% type A instructions, 13% type B instructions and 65% type C instructions?
(b) Let a machine M2 have average CPI = 2.7 and clock rate = 2.8 GHz. If the
CPI of a revised machine M3 is 1.2 times that of machine M2 , then how
much faster must the clock rate of machine M3 be for M3 to be 40% faster
than M2?
6 Explain what is meant by the following. You may use diagrams if appropriate:
(a) Sign extension in MIPS
(b) Base addressing
(c) Multicycle datapath and its advantages over single-cycle datapath
(d) Forwarding (in a pipeline)
(e) PC-relative addressing
7 For the pipelined MIPS datapath shown in Figure Q7, two lines are marked with an “X” .
(a) Describe, in words, the drawback of cutting line 1 relative to the working, unmodified processor. Give an example of code that will fail.
(b) Describe, in words, the drawback of cutting line 2 relative to the working, unmodified processor. Which of the following two segments of code will fail? Explain why.
add $s1, $t0, $t1
add $s1, $t2, $s1
and
add $s1, $t0, $t1
add $s1, $s1, $s1
Figure Q7
8 The three formats of the MIPS instruction set are shown in Figure Q8. The
Verilog code for the behavioural specification of an MIPS-Lite multi-cycle processor is shown as follows. Words 0-15 in the memory are used for instructions and words 16-31 in the memory are used for data storage. Read the Verilog code and answer the following questions:
(a) Explain the relevant operations for an LW instruction in the five clock
cycles and refer to the line numbers of the Verilog code.
(c) Explain what these variables represent in the processor: IR[15:0], (6)
Memory[PC>>2], Regs[IR[20:16]].
Figure Q8
1 module CPU (clock, reset);
2 parameter R_Type = 6’b0, LW = 6'b100011, SW = 6'b101011,
3 BEQ=6'b000100, J=6’d2;
4 input clock, reset; //external inputs
5 reg [31:0] PC, Regs[0:31], Memory [0:31], IR, ALUOut, MDR,
6 A, B;
7 reg [2:0] state; // processor state
8 wire [5:0] opcode;
9 wire [31:0] SignExtend,PCOffset;
10 assign opcode = IR[31:26];
11 assign SignExtend = {{16{IR[15]}},IR[15:0]};
12 assign PCOffset = SignExtend << 2;
13 // set the PC to 0 and start the control in state 1
14 initial begin PC = 0; state = 1; end
15
16 always @(posedge clock or posedge reset) begin
17 Regs[0] = 0; // to make sure R0 is always 0
18
19 if (reset) begin
20 PC = 0;
21 state = 1;
22 Memory[16]=32'h00000005; // words 16-31 used
23 Memory[17]=32'h0000000B; // for data memory 24 // words 0-15 used
25 // for instruction memory
26 end 27
28 case (state) 29 1: begin
30 IR <= Memory[PC>>2];
31 PC <= PC + 4;
32 state=2;
33 end
34
35 2: begin
36 A <= Regs[IR[25:21]];
37 B <= Regs[IR[20:16]];
38 ALUOut <= PC + PCOffset;
39 state= 3;
40 end 41
42
43 3: begin //
44 state =4;
45 if ((opcode==LW) | (opcode==SW))
46 ALUOut <= A + SignExtend;
47 else if (opcode == R_Type)
48 case (IR[5:0])
49 32: ALUOut= A + B;
50 default: ALUOut= A; //other ALU operations
51 endcase
52 else if (opcode == BEQ)
53 begin
54 if (A==B) PC <= ALUOut;
55 state = 1;
56 end
57 else if (opocode == J)
58 begin
59 PC = {PC[31:28], IR[25:0],2'b00};
60 state = 1;
61 end
62 end
63
64 4: begin
65 if (opcode == R_Type) begin
66 Regs[IR[15:11]] <= ALUOut;
67 state =1;
68 end //R-type finishes
69 else if (opcode == LW) begin
70 MDR <= Memory[ALUOut>>2];
71 state =5;
72 end
73 else if (opcode == SW) begin
74 Memory[ALUOut>>2] <= B;
75 state = 1;
76 end
77 end
78
79 5: begin
80 Regs[IR[20:16]] = MDR;
81 state = 1;
82 end
83 endcase
84 end
85 endmodule
2023-01-04