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CS 370 Computer Architecture

Lab Assignment 2: Hamming Code Implementation

(100 points, weight 10%, due 11:59pm on October 17)

Goal:

The purpose of this project is to demonstrate the use of Boolean logic and build basic circuits. Note that this lab assignment is a group assignment with each group having 2 students. If you need help to find out a partner, please send an email to the grader.

Problem Statement:

The predominant storage inside a computer systems are on disks drives. SCSI disks are the standard disks in most Unix Workstations from Sun, HP, SGI, and other vendors. They are also the standard disks in Macintoshes and Higher-end Intel PC's, especially network servers. Consider the Wide Ultra4 SCSI, which transfers data packets in 16-bit bursts at 160 MHz with a maximum throughput of 320 MB/sec. The data transfers at higher rates can result in random-noise pulse changes from a 0 to 1 and 1 to a 0. As the speed of processors and electronic communications increases, these parity flips become more prevalent and the inability to detect when these errors occur can be fatal. As a Design Engineer you have been requested to create system for the transmission of these 8-bit packets from an I/O Controller to Memory using Error Correcting Code over 12-bit data bus line. Wide SCSI contains a 68-bit bus; however, for the sake of simplification we are only concerned with the data bits. The other bits in the SCSI bus are for bus arbitration, synchronization, power management, etc. In this project, we will use even parity.

	Memory		I/O Controller

Transmission Vectored Bit: A 4-Bit Parity Vector (P1-P4) are interlaced with the 8-bit

Data Vector (D1 :D8) and an additional parity bit P5 is appended to the 12-bit hamming code to ensure that the entire 13-bit vector is even parity:

P1 P2 D1 P3 D2 D3 D4 P4 D5 D6 D7 D8P5

1) Create an ECC Generator, at the I/O Controller from the 8-bit Data Vector. The output of the ECC Generator will be the 13-Bit Vector.

2) Construct a 13-bit Data Transmission bus to send the 8-bit binary data and 5 parity bits over to Memory.

3) Construct an ECC Detector at Main Memory that corrects for single bit errors. Generally an interrupt/error handler is used to handle errors from the OS, for this exercise we will use 3 Hex displays, 2 for data and 1 for an error status, for diagnostic purposes:

. In the event that no error has occurred, your design must display the data transferred using the 2 Hex data displays and a “0” as an error status.

. For single bit transmission errors, your system must correct the error and display the data along with “C” in the 3rd Hex Display.

. For 2-bit transmission errors, your design must display “E” in the error status display.

Submission Instructions:

1. Write a Readme text file that includes (1) your group member names and the contribution of each member (who did what); (2) list each file enclosed in your submission package and briefly explain its function and usage.

2. Submit your LogicWorks files including your circuit schematic file (.cct) and your library file (.clf).

3. In your .cct file, please document each section using the Text tool (Ctrl_E) so that the grader knows how it works. Note that documentation is essential for full credit.

4. Zip all your LogicWorks files and the Readme text file into one document and name it using the first initial and the last name of one of your group members. (e.g., assume that Nathan Adams is in your group, your zip file should be NAdams.zip). Note that only one member should submit this lab assignment on behalf of the entire group.

5. Submit your zip file from within the Canvas.

Common issues and some comments:

1. Make sure all circuit parts are completely connected. Sometimes parts can appear to be connected in logic works without actually being connected.

2. Do not directly connect to wires that can have different values. Instead, connect them through a gate to prevent the value from being a C.

3. The checking bits show the position of the error bit, not which data bit is an error. For example C8’C4C2’C1 indicates a bit error at position 5, which is the second data bit.

4. For any binary value Z, Z xor 0 = Z and Z xor 1 = Z’ . This is why it is easy to use xor gates to switch or not switch binary values.

5. Students should not submit separate .cct files for each part. Instead, make sure all parts are connected in a final circuit and submit that .cct file.

Rubric:

Testing Cases:

1. No error occurs

2. A one-bit error occurs

3. A two-bit error occurs

Partner Rules:

1. One student is required to develop the ECC Generator while the other student is expected to complete the ECC Detector.

	Correctness	Logic
ECC Generator (30%) Generated 12 bits (10%)	If the ECC part works as intended, you will receive 20 points.	If the logic for the ECC generator is correct, you will receive 10 points.
Data Transmission (10%)	If the Data Transmission part works as intended, you will receive 5 points.	If the logic for the Data Transmission is correct, you will receive 5 points.
Main Memory (50%) Finding C (30%) Flipping incorrect bit (10%) Status Display and P (10%)	If the Main Memory part works as intended, you will receive 20 points.	If the logic for the Main Memory is correct, you will receive 10 points.
Documentation (10%)		You will receive 10 points by providing good descriptive documentation.