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SEMESTER ONE 2022

PHYSICS

Digital Fundamentals


Question 1

(a)  Write the decimal numbers 30 and –30 as 7 bit 2’s complement numbers.                        (2 marks)

(b)  Add the two 2’s complement numbers from part (a) together, then express the result of this 2’s

complement addition as a signed decimal.                                                                           (2 marks)

(c)  What are fewest number of bits needed correctly represent the number –30 in a 2’s complement     system?     (2 marks)

(d)   Use a truth table to prove A + BC = (A + B)(A + C)                                                               (2 marks)

(e)  Use Boolean algebra to prove A + BC = (A + B)(A + C)                                                        (2 marks)

(f)   Complete the truth table for the output Q in the circuit shown below. (Note Q0  and Q0   are the

initial states of Q and Q ). Do not complete the full truth table, only the four elements shown. (4 marks)

 

(g)  Show how a gated SR latch can be built out of a standard SR latch and some logic gates. (2 marks)

(h)  Show how an edge-triggered D flip-flop can be built out of an edge-triggered SR flip-flop and a single logic gate.      (2 marks)

(i)   Sketch a circuit that uses two full-adders to add together two 2-bit binary numbers A2A1 + B2B1 (2 marks)

(j)   Explain in 2 or 3 sentences why the circuit from part (i) is called a ripple adder.              (2 marks)

 

(k)  Sketch a circuit that uses five full-adders to add together three 2-bit binary numbers:

A2A1 + B2B1 + C2C1                                                                                                                                                                    (3 marks)

Question 2

Shown below is the truth table for the output of a 7-segment display logic chip that takes as its input a 4-bit binary number, and outputs a single hexadecimal digit (0 through to F, as shown in red below).

The inputs are a 4-bit binary number ABCD. The outputs are a, b, c, d, e,f, and g, as labelled below.

 

(a)  Write down the truth table for the outputsf and g of this circuit.                                         (2 marks)

(b)  Write down an optimized sum of products (SOP) expression for the outputf.                  (3 marks)

(c)  Write down an optimized product of sums (POS) expression for the outputf.                  (3 marks)

(d)  Implement the SOP expression of part (b) using only AND, OR, and NOT gates.            (2 marks)

(e)  Implement the SOP expression of part (b) using only NAND gates.                                  (2 marks)

(f)   Shown below is a two button ‘Quiz buzzer’ circuit. Explain the operation of the circuit.   (2 marks)

 

(g)  The circuit in part (f) contains no option to reset the lights after one of the contestants has pressed

their button. Redraw the circuit to include a reset option.                                                    (4 marks)

(h)  A gated D latch has the truth table shown below. Show how this circuit can be implemented using

an SR latch and some additional

gates.

(3 marks)

 

(i)   Shown below is a master-slave D flip-flop made using two gated D latches:

 

Complete the following timing diagram for the outputs Q1 and Q. Both outputs start low. You will need to carefully copy this timing diagram onto your own answer sheet. (4 marks)

 

Question 3

Shown below is a schematic diagram of a general purpose asynchronous counter chip. The chip has a negative edge-triggered CLK input, and two additional asynchronous inputs labeled A and B. If the   inputs A and B are both HIGH an asynchronous CLR command resets all 3 flip-flops. Also shown    below is the symbol for this counter.

 

(a)  Explain in 2 or 3 sentences the drawbacks of using an asynchronous counter compared to using a

synchronous counter.

(2 marks)

(b)  Show how this chip can be wired up to act as a 3-bit asynchronous up-counter. Don’t draw the

circuit in full, just use the symbol for the chip (above right).                                               (2 marks)

(c)  Show how two of these chips can be wired up to act as a 6-bit asynchronous up-counter. Again,     don’t draw the circuit in full, just use the symbol for the chips (above right).                     (2 marks)

(d)  Show how one of these chips can be wired up to act as a 3-bit asynchronous up-counter that counts from 0 to 5, then resets to 0 immediately the counter reaches 6. Again, don’t draw the circuit in      full, just use the symbol for the chip (above right).                                                              (2 marks)

(e) Draw the timing diagram for the outputs Q2, Q1 and Q0 of the circuit in part (d). Assume all outputs

start low. Use the input CLK sequence shown below.                                                          (3 marks)

 

(f)  Show how D-flip flops can be added to this circuit to remove any glitches by ‘strobing’ the output. (2 marks)

(g) In the below circuit Q4Q3Q2Q1Q0 = 10010 initially.

 

(i)  What will Q4Q3Q2Q1Q0 be six clock pulses later?

(ii) How many different states of Q4Q3Q2Q1Q0 are possible with this circuit?

(iii) If the clock frequency is 2 MHz (2×106 Hz), what is the time delay for a logic level that has just been outputted at Q0 to travel through to the output Q4? Assume time delays inside the D flip-

flops are negligible (i.e. neglect gate propagation delays).                                           (2 marks)

(h)  You have been given the task of designing a decoder that detects the presence of the codes 0000,

0011, 1101, 1000 and 1011 (of form Q4Q3Q2Q1). An active HIGH output is required to indicate   their presence. Develop the minimum decoding logic with a single output that will indicate when any one of these codes is on the inputs. For any other code, the output must be LOW. Draw the

circuit that you will use to decode these signals in the decoder box.                                  (6 marks)

 

Question 4

We wish to build a 3-bit synchronous counter using edge-triggered J-K flip-flops with outputs Q3, Q2, and Q1 . A schematic diagram (minus the logic for the flip-flop inputs) is shown below:

 

The counter must output the following sequence of decimal numbers in 3-bit binary and then repeat:

4 t 7 t 5 t 1 t 3 t … .

The output of the counter is Q3Q2Q1 . If the counter starts or gets into an illegal state it should return to 4 after the next clock pulse.

(a) Write down the state diagram for this counter. Make sure you include the illegal states.     (2 marks) (b) Write down the next state table for this counter. Make sure you include the illegal states.  (2 marks)

(c) Work out the optimized sum of products logical expressions for the flip-flop inputs J1 and K1 . (6 marks)

(d)  Draw the circuit diagram of the circuit (logic gates and inputs) whose output is connected to the flip-flop input K1 in order for this counter to work (i.e. count the repeating sequence

4 t 7 t 5 t 1 t 3 and resets the counter to 4 if it finds itself in an illegal state).          (2 marks)

A synchronous counter is now made of D flip-flops as shown below. This counter has the same           repeating counting sequence as the counter above (4 t 7 t 5 t 1 t 3 t … .) but this time it is        assumed that the counter will never get into an illegal state so there is no need to have additional logic to make the counter reset to 4 if it gets into an illegal state.

 

(e)  Write down the D flip-flop transistion table.                                                                        (2 marks)

(f)   Work out the optimized sum of products logical expressions for the D flip-flop input D2 (this is the

flip-flop that has output Q2).                                                                                                 (4 marks)

(g) The diagram below shows a 3-bit counter designed so that it does not sequence through the entire 8

binary states. Determine its counting sequence (Q3Q2Q1). Assume initially that Q3Q2Q1 = 111.

 

(3 marks)

(h)  Complete the Data out waveform of the below shift register with the given D inputs (these D

inputs stay constant). Use the SHIFT and LOAD and clock pulses shown in the box. Assume that the register has been initially preset to logical 0 i.e. all the outputs of the flip flops in the register  are initially at logic 0. You will need to carefully copy this timing diagram onto your own answer

sheet.                                                                                                                                      (4 marks)

 

Question 5:

(a)   The below circuit shows how a 74HC151 multiplexer can be used to generate waveforms with any

desired pattern. The pattern is programmed using eight switches as shown, and the waveform is produced by pulsing the MOD-8 up counter with a clock signal. S2 is the most significant input variable bit (MSB) and S0 the LSB.

 

Copy the below timing diagram onto your own answer sheet and on it draw the output waveform at Z for the given switch positions. Assume that the counter is at 000 before the first clock pulse shown on

the timing diagram.                                                                                                                           (4 marks)

 

(b)   Draw a careful sketch of how you would programme the 74HC151 multiplexer to implement the SOP Boolean expression:  Z = S2 S1S0  + S2 S1 S0  + S2 S1 S0  + S2 S1S0  . S2 is the most significant input

variable bit (MSB).                                                                                                               (4 marks)

(c)  You have a demultiplexer that has a eight bit data select switch (i.e. 8 data select lines). What is     the maximum number of data out lines that this demultiplexer can have? Why can’t it have more    than this?   (2 marks)

(d)  A demultiplexer is shown below. Copy the below timing diagram onto your own answer sheet and on it sketch the data outputs D0 to D3 . The Data select lines are S1S0 . S1 is the MSB.         (5 marks)

 

(e)  Below is the logic diagram for a bidirectional shift register:

 

Copy the below timing diagram onto your own answer sheet and on it sketch the outputs for Q0, Q1, Q2 and Q3  for the clock (CLK) and Right/ Left  input waveforms shown below. Initially Q3Q2Q1Q0 have been pre-set to 0100 (as shown in the below graphs). The Serial Data in line is connected to logical 1. (6 marks)

 

(f)  For the bidirectional shift register in (e), describe two methods to make the Q outputs initially preset

to Q3Q2Q1Q0 = 0100 using (i) clock pulses and (ii) asynchronous inputs (not shown on the logic

diagram in (d)).                                                                                                                     (4 marks)