CSE 320 HW 4
Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: daixieit
CSE 320 HW 4
2021
1. Figure 1 shows a block diagram of a 4-bit twos complement multiplier, that is also described in the notes and the textbook. It employs a combined add-shift operation in which the shift operation that follows an addition is performed in the same step by wiring.
Figure 1: 4-bit, Twos Complement Multiplier
You are write and simulate a Verilog description (either a 2-segment or 3-segment) of an N- bit, twos complement multiplier based on the design shown in Figure 1. The design as shown consists of two main components:
1. a controller, which is a finite state machine, and
2. a datapath, which consists of a specialized shift register, an N-bit adder, a complementer, a counter and possibly other functional units.
● The top module, named Mult2C, should instantiate the two main components – the con- troller, named MultC CTRL, and the datapath, named Mult2C DP, and establish the necessary connections. Mult2C should include an explicit synchronous reset input RE- SET along with a start input ST.
● Follow the methodology described in the notes and explained in class: For each register write a simple sequential always block that updates the contents of the register with whatever data is on its inputs on a clock edge. Then, for each input to a register, write a combinational always block that continuously computes the input to every register. This basic methodology can be applied to both the controller and the datapath unit.
● To simplify the task, use synthesizeable behavioral Verilog constructs as much as possible, while constructing the module that adheres to the structure shown in Figure 1.
● Write a testbench and simulate your design as follows.
– Note: Since your design should work correctly for any N , you have to include a counter in the datapath unit which will issue an output, K = 1 when the full count is reached. The controller stops the computation when K = 1 and the product should be in the AC-MQ register.
– Generate a clock waveform with a 50% duty cycle.
– For each input, reset the machine on the first clock cycle (apply it on the falling edge of the clock), then assert the start signal on cycle 2 (also on the falling edge of the clock).
– Test your design for the following values of X (multiplier) and Y (multiplicand), n = 4, 8, 16, 32.
– Display your results in a tabular form as shown below.
|
X Y |
X Y |
|
X Y |
|
X Y |
|
|
|
-1 -1 |
-2n − 1 2n − 1 - 1 |
|
-2n − 1 |
-(2n − 1 - 1) |
|
2n − 1 - 1 2n − 1 - 1 |
|
X * Y |
|
|
|
|
|
X Y |
|
X Y |
X Y |
X Y |
|
||
|
2n/2 2n/2 |
|
-2n/2 |
-2n/2 |
2n/2 -2n − 1 |
2n − 1 - 1 |
-2n/2 |
|
X * Y |
|
|
|
|
Submission Instructions:
1. Verilog source files named CSE320-2022-FA-HW4-LastName-FirstName-2CMult.v
2. A PDF file named CSE320-2022-FA-HW4-LastName-FirstName-Results.pdf which contains all three tables correctly labeled and numbered.
3. Place the files in gziped folder named CSE320-2022-FA-HW4-LastName-FirstName.zip
2022-11-04